^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _SPARC64_UPA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _SPARC64_UPA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/asi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* UPA level registers and defines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* UPA Config Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define UPA_CONFIG_RESV 0xffffffffc0000000 /* Reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define UPA_CONFIG_PCON 0x000000003fc00000 /* Depth of various sys queues. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define UPA_CONFIG_MID 0x00000000003e0000 /* Module ID. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define UPA_CONFIG_PCAP 0x000000000001ffff /* Port Capabilities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* UPA Port ID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define UPA_PORTID_FNP 0xff00000000000000 /* Hardcoded to 0xfc on ultra. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define UPA_PORTID_RESV 0x00fffff800000000 /* Reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define UPA_PORTID_ECCVALID 0x0000000400000000 /* Zero if mod can generate ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define UPA_PORTID_ONEREAD 0x0000000200000000 /* Set if mod generates P_RASB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define UPA_PORTID_PINTRDQ 0x0000000180000000 /* # outstanding P_INT_REQ's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define UPA_PORTID_PREQDQ 0x000000007e000000 /* slave-wr's to mod supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define UPA_PORTID_PREQRD 0x0000000001e00000 /* # incoming P_REQ's supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define UPA_PORTID_UPACAP 0x00000000001f0000 /* UPA capabilities of mod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define UPA_PORTID_ID 0x000000000000ffff /* Module Identification bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* UPA I/O space accessors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static inline unsigned char _upa_readb(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned char ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __asm__ __volatile__("lduba\t[%1] %2, %0\t/* upa_readb */"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) : "=r" (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static inline unsigned short _upa_readw(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned short ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) __asm__ __volatile__("lduha\t[%1] %2, %0\t/* upa_readw */"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) : "=r" (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static inline unsigned int _upa_readl(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* upa_readl */"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) : "=r" (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static inline unsigned long _upa_readq(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* upa_readq */"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) : "=r" (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static inline void _upa_writeb(unsigned char b, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __asm__ __volatile__("stba\t%0, [%1] %2\t/* upa_writeb */"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) : "r" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline void _upa_writew(unsigned short w, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __asm__ __volatile__("stha\t%0, [%1] %2\t/* upa_writew */"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline void _upa_writel(unsigned int l, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __asm__ __volatile__("stwa\t%0, [%1] %2\t/* upa_writel */"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) : "r" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static inline void _upa_writeq(unsigned long q, unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __asm__ __volatile__("stxa\t%0, [%1] %2\t/* upa_writeq */"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) : "r" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define upa_readb(__addr) (_upa_readb((unsigned long)(__addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define upa_readw(__addr) (_upa_readw((unsigned long)(__addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define upa_readl(__addr) (_upa_readl((unsigned long)(__addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define upa_readq(__addr) (_upa_readq((unsigned long)(__addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define upa_writeb(__b, __addr) (_upa_writeb((__b), (unsigned long)(__addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define upa_writew(__w, __addr) (_upa_writew((__w), (unsigned long)(__addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define upa_writel(__l, __addr) (_upa_writel((__l), (unsigned long)(__addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define upa_writeq(__q, __addr) (_upa_writeq((__q), (unsigned long)(__addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif /* __KERNEL__ && !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif /* !(_SPARC64_UPA_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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