^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * turbosparc.h: Defines specific to the TurboSparc module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This is SRMMU stuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SPARC_TURBOSPARC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SPARC_TURBOSPARC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/asi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/pgtsrmmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Bits in the SRMMU control register for TurboSparc modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * -------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * |impl-vers| RSV| PMC |PE|PC| RSV |BM| RFR |IC|DC|PSO|RSV|ICS|NF|ME|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * -------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 31 24 23-21 20-19 18 17 16-15 14 13-10 9 8 7 6-3 2 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * BM: Boot Mode -- 0 = not in boot mode, 1 = in boot mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * This indicates whether the TurboSparc is in boot-mode or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * IC: Instruction Cache -- 0 = off, 1 = on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * DC: Data Cache -- 0 = off, 1 = 0n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * These bits enable the on-cpu TurboSparc split I/D caches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * ICS: ICache Snooping -- 0 = disable, 1 = enable snooping of icache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * NF: No Fault -- 0 = faults generate traps, 1 = faults don't trap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TURBOSPARC_MMUENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TURBOSPARC_NOFAULT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TURBOSPARC_ICSNOOP 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TURBOSPARC_PSO 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TURBOSPARC_DCENABLE 0x00000100 /* Enable data cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TURBOSPARC_ICENABLE 0x00000200 /* Enable instruction cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TURBOSPARC_BMODE 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TURBOSPARC_PARITYODD 0x00020000 /* Parity odd, if enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TURBOSPARC_PCENABLE 0x00040000 /* Enable parity checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Bits in the CPU configuration register for TurboSparc modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * -------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * |IOClk|SNP|AXClk| RAH | WS | RSV |SBC|WT|uS2|SE|SCC|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * -------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 31 30 29-28 27-26 25-23 22-8 7-6 5 4 3 2-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TURBOSPARC_SCENABLE 0x00000008 /* Secondary cache enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TURBOSPARC_uS2 0x00000010 /* Swift compatibility mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TURBOSPARC_WTENABLE 0x00000020 /* Write thru for dcache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TURBOSPARC_SNENABLE 0x40000000 /* DVMA snoop enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Bits [13:5] select one of 512 instruction cache tags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline void turbosparc_inv_insn_tag(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) : "r" (addr), "i" (ASI_M_TXTC_TAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Bits [13:5] select one of 512 data cache tags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static inline void turbosparc_inv_data_tag(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) : "r" (addr), "i" (ASI_M_DATAC_TAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline void turbosparc_flush_icache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) for (addr = 0; addr < 0x4000; addr += 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) turbosparc_inv_insn_tag(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline void turbosparc_flush_dcache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) for (addr = 0; addr < 0x4000; addr += 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) turbosparc_inv_data_tag(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static inline void turbosparc_idflash_clear(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) for (addr = 0; addr < 0x4000; addr += 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) turbosparc_inv_insn_tag(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) turbosparc_inv_data_tag(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline void turbosparc_set_ccreg(unsigned long regval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __asm__ __volatile__("sta %0, [%1] %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static inline unsigned long turbosparc_get_ccreg(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __asm__ __volatile__("lda [%1] %2, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) : "=r" (regval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) : "r" (0x600), "i" (ASI_M_MMUREGS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif /* !(_SPARC_TURBOSPARC_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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