Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * tsunami.h:  Module specific definitions for Tsunami V8 Sparcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _SPARC_TSUNAMI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _SPARC_TSUNAMI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/asi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* The MMU control register on the Tsunami:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * -----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * -----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  *  31      24 23 22 21 20 19-18 17  16 14  13-12 11 10-9  8  7 6-2  1  0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * SW: Enable Software Table Walks  0=off 1=on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * AV: Address View bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * DV: Data View bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * MV: Memory View bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * PC: Parity Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * ITD: ITBR disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * ALC: Alternate Cacheable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * PE: Parity Enable   0=off 1=on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * RC: Refresh Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  * IE: Instruction cache Enable  0=off 1=on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * DE: Data cache Enable  0=off 1=on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  * NF: No Fault, same as all other SRMMUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)  * ME: MMU Enable, same as all other SRMMUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TSUNAMI_SW        0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TSUNAMI_AV        0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TSUNAMI_DV        0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TSUNAMI_MV        0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TSUNAMI_PC        0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TSUNAMI_ITD       0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TSUNAMI_ALC       0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TSUNAMI_PE        0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TSUNAMI_RCMASK    0x00000C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TSUNAMI_IENAB     0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TSUNAMI_DENAB     0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TSUNAMI_NF        0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TSUNAMI_ME        0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static inline void tsunami_flush_icache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			     : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			     : "i" (ASI_M_IC_FLCLEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			     : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static inline void tsunami_flush_dcache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			     : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 			     : "i" (ASI_M_DC_FLCLEAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 			     : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif /* !(_SPARC_TSUNAMI_H) */