^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* swift.h: Specific definitions for the _broken_ Swift SRMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MMU module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SPARC_SWIFT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SPARC_SWIFT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Swift is so brain damaged, here is the mmu control register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SWIFT_ST 0x00800000 /* SW tablewalk enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SWIFT_WP 0x00400000 /* Watchpoint enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Branch folding (buggy, disable on production systems!) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SWIFT_BF 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SWIFT_PMC 0x00180000 /* Page mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SWIFT_PE 0x00040000 /* Parity enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SWIFT_PC 0x00020000 /* Parity control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SWIFT_AP 0x00010000 /* Graphics page mode control (TCX/SX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SWIFT_BM 0x00004000 /* Boot mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SWIFT_RC 0x00003c00 /* DRAM refresh control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SWIFT_IE 0x00000200 /* Instruction cache enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SWIFT_DE 0x00000100 /* Data cache enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SWIFT_SA 0x00000080 /* Store Allocate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SWIFT_NF 0x00000002 /* No fault mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SWIFT_EN 0x00000001 /* MMU enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Bits [13:5] select one of 512 instruction cache tags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static inline void swift_inv_insn_tag(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) : "r" (addr), "i" (ASI_M_TXTC_TAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Bits [12:4] select one of 512 data cache tags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static inline void swift_inv_data_tag(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) : "r" (addr), "i" (ASI_M_DATAC_TAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static inline void swift_flush_dcache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) for (addr = 0; addr < 0x2000; addr += 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) swift_inv_data_tag(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline void swift_flush_icache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) for (addr = 0; addr < 0x4000; addr += 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) swift_inv_insn_tag(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline void swift_idflash_clear(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) for (addr = 0; addr < 0x2000; addr += 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) swift_inv_insn_tag(addr<<1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) swift_inv_data_tag(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Swift is so broken, it isn't even safe to use the following. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline void swift_flush_page(unsigned long page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) : "r" (page), "i" (ASI_M_FLUSH_PAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static inline void swift_flush_segment(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) : "r" (addr), "i" (ASI_M_FLUSH_SEG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline void swift_flush_region(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) : "r" (addr), "i" (ASI_M_FLUSH_REGION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static inline void swift_flush_context(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) : "i" (ASI_M_FLUSH_CTX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif /* !(_SPARC_SWIFT_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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