^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * include/asm/sunbpp.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _ASM_SPARC_SUNBPP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _ASM_SPARC_SUNBPP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) struct bpp_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* DMA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) __volatile__ __u32 p_csr; /* DMA Control/Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) __volatile__ __u32 p_addr; /* Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) __volatile__ __u32 p_bcnt; /* Byte Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) __volatile__ __u32 p_tst_csr; /* Test Control/Status (DMA2 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Parallel Port registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) __volatile__ __u16 p_hcr; /* Hardware Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) __volatile__ __u16 p_ocr; /* Operation Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) __volatile__ __u8 p_dr; /* Parallel Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) __volatile__ __u8 p_tcr; /* Transfer Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) __volatile__ __u8 p_or; /* Output Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) __volatile__ __u8 p_ir; /* Input Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) __volatile__ __u16 p_icr; /* Interrupt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* P_HCR. Time is in increments of SBus clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* P_OCR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define P_OCR_MEM_CLR 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define P_OCR_DATA_SRC 0x4000 /* ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define P_OCR_ACK_DSEL 0x0800 /* ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define P_OCR_EN_DIAG 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define P_OCR_BUSY_OP 0x0200 /* Busy operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define P_OCR_ACK_OP 0x0100 /* Ack operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* P_TCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define P_TCR_DIR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define P_TCR_BUSY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define P_TCR_ACK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define P_TCR_DS 0x01 /* Strobe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* P_OR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define P_OR_V3 0x20 /* ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define P_OR_V2 0x10 /* ) on Zebra only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define P_OR_V1 0x08 /* ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define P_OR_INIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define P_OR_AFXN 0x02 /* Auto Feed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define P_OR_SLCT_IN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* P_IR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define P_IR_PE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define P_IR_SLCT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define P_IR_ERR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* P_ICR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define P_DS_IRQ 0x8000 /* RW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define P_ACK_IRQ 0x4000 /* RW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define P_BUSY_IRQ 0x2000 /* RW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define P_PE_IRQ 0x1000 /* RW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define P_SLCT_IRQ 0x0800 /* RW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define P_ERR_IRQ 0x0400 /* RW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define P_BUSY_IRP 0x0080 /* RW 1= rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define P_BUSY_IRQ_EN 0x0040 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define P_PE_IRP 0x0020 /* RW 1= rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define P_PE_IRQ_EN 0x0010 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define P_SLCT_IRP 0x0008 /* RW 1= rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define P_SLCT_IRQ_EN 0x0004 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define P_ERR_IRP 0x0002 /* RW1 1= rising edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define P_ERR_IRQ_EN 0x0001 /* RW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif /* !(_ASM_SPARC_SUNBPP_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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