^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _SPARC64_SPITFIRE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _SPARC64_SPITFIRE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifdef CONFIG_SPARC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/asi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* The following register addresses are accessible via ASI_DMMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * and ASI_IMMU, that is there is a distinct and unique copy of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * each these registers for each TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TSB_TAG_TARGET 0x0000000000000000 /* All chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TLB_SFSR 0x0000000000000018 /* All chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TSB_REG 0x0000000000000028 /* All chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TLB_TAG_ACCESS 0x0000000000000030 /* All chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VIRT_WATCHPOINT 0x0000000000000038 /* All chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PHYS_WATCHPOINT 0x0000000000000040 /* All chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TSB_EXTENSION_P 0x0000000000000048 /* Ultra-III and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TSB_EXTENSION_S 0x0000000000000050 /* Ultra-III and later, D-TLB only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TSB_EXTENSION_N 0x0000000000000058 /* Ultra-III and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TLB_TAG_ACCESS_EXT 0x0000000000000060 /* Ultra-III+ and later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* These registers only exist as one entity, and are accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * via ASI_DMMU only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PRIMARY_CONTEXT 0x0000000000000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SECONDARY_CONTEXT 0x0000000000000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DMMU_SFAR 0x0000000000000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VIRT_WATCHPOINT 0x0000000000000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PHYS_WATCHPOINT 0x0000000000000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPITFIRE_HIGHEST_LOCKED_TLBENT (64 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CHEETAH_HIGHEST_LOCKED_TLBENT (16 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define L1DCACHE_SIZE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SUN4V_CHIP_INVALID 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SUN4V_CHIP_NIAGARA1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SUN4V_CHIP_NIAGARA2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SUN4V_CHIP_NIAGARA3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUN4V_CHIP_NIAGARA4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SUN4V_CHIP_NIAGARA5 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SUN4V_CHIP_SPARC_M6 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SUN4V_CHIP_SPARC_M7 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SUN4V_CHIP_SPARC_M8 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SUN4V_CHIP_SPARC64X 0x8a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SUN4V_CHIP_SPARC_SN 0x8b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SUN4V_CHIP_UNKNOWN 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * The following CPU_ID_xxx constants are used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * to identify the CPU type in the setup phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * (see head_64.S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CPU_ID_NIAGARA1 ('1')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CPU_ID_NIAGARA2 ('2')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CPU_ID_NIAGARA3 ('3')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CPU_ID_NIAGARA4 ('4')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CPU_ID_NIAGARA5 ('5')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CPU_ID_M6 ('6')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CPU_ID_M7 ('7')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CPU_ID_M8 ('8')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CPU_ID_SONOMA1 ('N')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) enum ultra_tlb_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) spitfire = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) cheetah = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) cheetah_plus = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) hypervisor = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) extern enum ultra_tlb_layout tlb_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) extern int sun4v_chip_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) extern int cheetah_pcache_forced_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void cheetah_enable_pcache(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define sparc64_highest_locked_tlbent() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) (tlb_type == spitfire ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SPITFIRE_HIGHEST_LOCKED_TLBENT : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) CHEETAH_HIGHEST_LOCKED_TLBENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) extern int num_kernel_image_mappings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* The data cache is write through, so this just invalidates the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * specified line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __asm__ __volatile__("stxa %0, [%1] %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) : /* No outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) : "r" (tag), "r" (addr), "i" (ASI_DCACHE_TAG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* The instruction cache lines are flushed with this, but note that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * this does not flush the pipeline. It is possible for a line to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * get flushed but stale instructions to still be in the pipeline,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * a flush instruction (to any address) is sufficient to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * this issue after the line is invalidated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __asm__ __volatile__("stxa %0, [%1] %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) : /* No outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) : "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline unsigned long spitfire_get_dtlb_data(int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __asm__ __volatile__("ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) : "=r" (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) : "r" (entry << 3), "i" (ASI_DTLB_DATA_ACCESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Clear TTE diag bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) data &= ~0x0003fe0000000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static inline unsigned long spitfire_get_dtlb_tag(int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __asm__ __volatile__("ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) : "=r" (tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) : "r" (entry << 3), "i" (ASI_DTLB_TAG_READ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) __asm__ __volatile__("stxa %0, [%1] %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) : /* No outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) : "r" (data), "r" (entry << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) "i" (ASI_DTLB_DATA_ACCESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static inline unsigned long spitfire_get_itlb_data(int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __asm__ __volatile__("ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) : "=r" (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) : "r" (entry << 3), "i" (ASI_ITLB_DATA_ACCESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Clear TTE diag bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) data &= ~0x0003fe0000000000UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static inline unsigned long spitfire_get_itlb_tag(int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) __asm__ __volatile__("ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) : "=r" (tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) : "r" (entry << 3), "i" (ASI_ITLB_TAG_READ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static inline void spitfire_put_itlb_data(int entry, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __asm__ __volatile__("stxa %0, [%1] %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) : /* No outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) : "r" (data), "r" (entry << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "i" (ASI_ITLB_DATA_ACCESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) : /* No outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) : "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) : /* No outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) : "r" (page | 0x20), "i" (ASI_IMMU_DEMAP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Cheetah has "all non-locked" tlb flushes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline void cheetah_flush_dtlb_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) : /* No outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) : "r" (0x80), "i" (ASI_DMMU_DEMAP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static inline void cheetah_flush_itlb_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) : /* No outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) : "r" (0x80), "i" (ASI_IMMU_DEMAP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Cheetah has a 4-tlb layout so direct access is a bit different.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * The first two TLBs are fully assosciative, hold 16 entries, and are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * used only for locked and >8K sized translations. One exists for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * data accesses and one for instruction accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * The third TLB is for data accesses to 8K non-locked translations, is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * 2 way assosciative, and holds 512 entries. The fourth TLB is for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * instruction accesses to 8K non-locked translations, is 2 way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * assosciative, and holds 128 entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Cheetah has some bug where bogus data can be returned from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * the problem for me. -DaveM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static inline unsigned long cheetah_get_ldtlb_data(int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) : "=r" (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) : "r" ((0 << 16) | (entry << 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "i" (ASI_DTLB_DATA_ACCESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static inline unsigned long cheetah_get_litlb_data(int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) : "=r" (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) : "r" ((0 << 16) | (entry << 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "i" (ASI_ITLB_DATA_ACCESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static inline unsigned long cheetah_get_ldtlb_tag(int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned long tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) __asm__ __volatile__("ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) : "=r" (tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) : "r" ((0 << 16) | (entry << 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "i" (ASI_DTLB_TAG_READ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static inline unsigned long cheetah_get_litlb_tag(int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned long tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) __asm__ __volatile__("ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) : "=r" (tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) : "r" ((0 << 16) | (entry << 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "i" (ASI_ITLB_TAG_READ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) __asm__ __volatile__("stxa %0, [%1] %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) : /* No outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) : "r" (data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "r" ((0 << 16) | (entry << 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "i" (ASI_DTLB_DATA_ACCESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static inline void cheetah_put_litlb_data(int entry, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __asm__ __volatile__("stxa %0, [%1] %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) : /* No outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) : "r" (data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "r" ((0 << 16) | (entry << 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "i" (ASI_ITLB_DATA_ACCESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) : "=r" (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_DATA_ACCESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned long tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) __asm__ __volatile__("ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) : "=r" (tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) : "r" ((tlb << 16) | (entry << 3)), "i" (ASI_DTLB_TAG_READ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) __asm__ __volatile__("stxa %0, [%1] %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) : /* No outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) : "r" (data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "r" ((tlb << 16) | (entry << 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "i" (ASI_DTLB_DATA_ACCESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static inline unsigned long cheetah_get_itlb_data(int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned long data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) __asm__ __volatile__("ldxa [%1] %2, %%g0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) : "=r" (data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) : "r" ((2 << 16) | (entry << 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "i" (ASI_ITLB_DATA_ACCESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static inline unsigned long cheetah_get_itlb_tag(int entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned long tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) __asm__ __volatile__("ldxa [%1] %2, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) : "=r" (tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) : "r" ((2 << 16) | (entry << 3)), "i" (ASI_ITLB_TAG_READ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static inline void cheetah_put_itlb_data(int entry, unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) __asm__ __volatile__("stxa %0, [%1] %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "membar #Sync"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) : /* No outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) : "r" (data), "r" ((2 << 16) | (entry << 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "i" (ASI_ITLB_DATA_ACCESS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #endif /* !(__ASSEMBLY__) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #endif /* CONFIG_SPARC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #endif /* !(_SPARC64_SPITFIRE_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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