^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sbi.h: SBI (Sbus Interface on sun4d) definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SPARC_SBI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SPARC_SBI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/obio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* SBI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct sbi_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* 0x0000 */ u32 cid; /* Component ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* 0x0004 */ u32 ctl; /* Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* 0x0008 */ u32 status; /* Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 _unused1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* 0x0010 */ u32 cfg0; /* Slot0 config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* 0x0014 */ u32 cfg1; /* Slot1 config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* 0x0018 */ u32 cfg2; /* Slot2 config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* 0x001c */ u32 cfg3; /* Slot3 config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* 0x0020 */ u32 stb0; /* Streaming buf control for slot 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* 0x0024 */ u32 stb1; /* Streaming buf control for slot 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* 0x0028 */ u32 stb2; /* Streaming buf control for slot 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* 0x002c */ u32 stb3; /* Streaming buf control for slot 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* 0x0030 */ u32 intr_state; /* Interrupt state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* 0x0034 */ u32 intr_tid; /* Interrupt target ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* 0x0038 */ u32 intr_diag; /* Interrupt diagnostics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SBI_CID 0x02800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SBI_CTL 0x02800004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SBI_STATUS 0x02800008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SBI_CFG0 0x02800010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SBI_CFG1 0x02800014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SBI_CFG2 0x02800018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SBI_CFG3 0x0280001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SBI_STB0 0x02800020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SBI_STB1 0x02800024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SBI_STB2 0x02800028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SBI_STB3 0x0280002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SBI_INTR_STATE 0x02800030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SBI_INTR_TID 0x02800034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SBI_INTR_DIAG 0x02800038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Burst bits for 8, 16, 32, 64 are in cfgX registers at bits 2, 3, 4, 5 respectively */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SBI_CFG_BURST_MASK 0x0000001e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* How to make devid from sbi no */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SBI2DEVID(sbino) ((sbino<<4)|2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* intr_state has 4 bits for slots 0 .. 3 and these bits are repeated for each sbus irq level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * +-------+-------+-------+-------+-------+-------+-------+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * SBUS IRQ LEVEL | 7 | 6 | 5 | 4 | 3 | 2 | 1 | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ Reser |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * SLOT # |3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0| ved |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Bits 31 27 23 19 15 11 7 3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static inline int acquire_sbi(int devid, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __asm__ __volatile__ ("swapa [%2] %3, %0" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "=r" (mask) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "0" (mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "i" (ASI_M_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline void release_sbi(int devid, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __asm__ __volatile__ ("sta %0, [%1] %2" : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "r" (mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "i" (ASI_M_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static inline void set_sbi_tid(int devid, int targetid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __asm__ __volatile__ ("sta %0, [%1] %2" : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "r" (targetid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "r" (ECSR_DEV_BASE(devid) | SBI_INTR_TID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "i" (ASI_M_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static inline int get_sbi_ctl(int devid, int cfgno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __asm__ __volatile__ ("lda [%1] %2, %0" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "=r" (cfg) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "i" (ASI_M_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline void set_sbi_ctl(int devid, int cfgno, int cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __asm__ __volatile__ ("sta %0, [%1] %2" : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "r" (cfg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "i" (ASI_M_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #endif /* !(_SPARC_SBI_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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