^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ross.h: Ross module specific definitions and defines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SPARC_ROSS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SPARC_ROSS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/asi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Ross made Hypersparcs have a %psr 'impl' field of '0001'. The 'vers'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * field has '1111'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* The MMU control register fields on the HyperSparc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * -----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * -----------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 31 24 23-22 21 20 19 18-15 14 13 12 11 10 9 8 7-2 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Phew, lots of fields there ;-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * CWR: Cache Wrapping Enabled, if one cache wrapping is on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * SE: Snoop Enable, turns on bus snooping for cache activity if one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * WBE: Write Buffer Enable, one turns it on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * MID: The ModuleID of the chip for MBus transactions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * BM: Boot-Mode. One indicates the MMU is in boot mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * C: Indicates whether accesses are cachable while the MMU is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * CS: Cache Size -- 0 = 128k, 1 = 256k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * MR: Memory Reflection, one indicates that the memory bus connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * to the MBus supports memory reflection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * CM: Cache Mode -- 0 = write-through, 1 = copy-back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * CE: Cache Enable -- 0 = no caching, 1 = cache is on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * NF: No Fault -- 0 = faults trap the CPU from supervisor mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 1 = faults from supervisor mode do not generate traps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HYPERSPARC_CWENABLE 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HYPERSPARC_SBENABLE 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HYPERSPARC_WBENABLE 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HYPERSPARC_MIDMASK 0x00078000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HYPERSPARC_BMODE 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HYPERSPARC_ACENABLE 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HYPERSPARC_CSIZE 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HYPERSPARC_MRFLCT 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HYPERSPARC_CMODE 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HYPERSPARC_CENABLE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HYPERSPARC_NFAULT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HYPERSPARC_MENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* The ICCR instruction cache register on the HyperSparc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * -----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * | | FTD | ICE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * -----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * 31 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * This register is accessed using the V8 'wrasr' and 'rdasr'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * opcodes, since not all assemblers understand them and those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * that do use different semantics I will just hard code the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * instruction with a '.word' statement.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * FTD: If set to one flush instructions executed during an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * instruction cache hit occurs, the corresponding line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * for said cache-hit is invalidated. If FTD is zero,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * an unimplemented 'flush' trap will occur when any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * flush is executed by the processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * ICE: If set to one, the instruction cache is enabled. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * zero, the cache will not be used for instruction fetches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * All other bits are read as zeros, and writes to them have no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * effect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Wheee, not many assemblers understand the %iccr register nor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * the generic asr r/w instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * 1000 0011 0100 0111 1100 0000 0000 0000 ! rd %iccr, %g1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * 0x 8 3 4 7 c 0 0 0 ! 0x8347c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * 1011 1111 1000 0000 0110 0000 0000 0000 ! wr %g1, 0x0, %iccr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * 0x b f 8 0 6 0 0 0 ! 0xbf806000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HYPERSPARC_ICCR_FTD 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HYPERSPARC_ICCR_ICE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static inline unsigned int get_ross_icr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int icreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __asm__ __volatile__(".word 0x8347c000\n\t" /* rd %iccr, %g1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "mov %%g1, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) : "=r" (icreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) : /* no inputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) : "g1", "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return icreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline void put_ross_icr(unsigned int icreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __asm__ __volatile__("or %%g0, %0, %%g1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ".word 0xbf806000\n\t" /* wr %g1, 0x0, %iccr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "nop\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "nop\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "nop\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) : "r" (icreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) : "g1", "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* HyperSparc specific cache flushing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* This is for the on-chip instruction cache. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static inline void hyper_flush_whole_icache(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) : "i" (ASI_M_FLUSH_IWHOLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) extern int vac_cache_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) extern int vac_line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline void hyper_clear_all_tags(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) for(addr = 0; addr < vac_cache_size; addr += vac_line_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) : "r" (addr), "i" (ASI_M_DATAC_TAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static inline void hyper_flush_unconditional_combined(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) : "r" (addr), "i" (ASI_M_FLUSH_CTX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static inline void hyper_flush_cache_user(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) for (addr = 0; addr < vac_cache_size; addr += vac_line_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) : "r" (addr), "i" (ASI_M_FLUSH_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline void hyper_flush_cache_page(unsigned long page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned long end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) page &= PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) end = page + PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) while (page < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) : /* no outputs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) : "r" (page), "i" (ASI_M_FLUSH_PAGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) page += vac_line_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif /* !(__ASSEMBLY__) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #endif /* !(_SPARC_ROSS_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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