^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pcic.h: JavaEngine 1 specific PCI definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998 V. Roganov and G. Raiko
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __SPARC_PCIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __SPARC_PCIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/pbm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct linux_pcic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) void __iomem *pcic_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned long pcic_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) void __iomem *pcic_config_space_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) void __iomem *pcic_config_space_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct resource pcic_res_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct resource pcic_res_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct resource pcic_res_cfg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct resource pcic_res_cfg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct linux_pbm_info pbm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct pcic_ca2irq *pcic_imap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int pcic_imdim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifdef CONFIG_PCIC_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int pcic_present(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int pcic_probe(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void pci_time_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void sun4m_pci_init_IRQ(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static inline int pcic_present(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static inline int pcic_probe(void) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline void pci_time_init(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static inline void sun4m_pci_init_IRQ(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Size of PCI I/O space which we relocate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCI_SPACE_SIZE 0x1000000 /* 16 MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* PCIC Register Set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCI_DIAGNOSTIC_0 0x40 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCI_SIZE_0 0x44 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCI_SIZE_1 0x48 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCI_SIZE_2 0x4c /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCI_SIZE_3 0x50 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCI_SIZE_4 0x54 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCI_SIZE_5 0x58 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCI_PIO_CONTROL 0x60 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCI_DVMA_CONTROL 0x62 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCI_DVMA_CONTROL_INACTIVITY_REQ (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCI_DVMA_CONTROL_IOTLB_ENABLE (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCI_DVMA_CONTROL_IOTLB_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCI_DVMA_CONTROL_INACTIVITY_ACK (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCI_INTERRUPT_CONTROL 0x63 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCI_CPU_INTERRUPT_PENDING 0x64 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCI_DIAGNOSTIC_1 0x68 /* 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCI_SOFTWARE_INT_CLEAR 0x6a /* 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCI_SOFTWARE_INT_SET 0x6e /* 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCI_SYS_INT_PENDING 0x70 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCI_SYS_INT_PENDING_PIO 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCI_SYS_INT_PENDING_DMA 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCI_SYS_INT_PENDING_PCI 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCI_SYS_INT_PENDING_APSR 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCI_SYS_INT_TARGET_MASK 0x74 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCI_SYS_INT_TARGET_MASK_CLEAR 0x78 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PCI_SYS_INT_TARGET_MASK_SET 0x7c /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCI_SYS_INT_PENDING_CLEAR 0x83 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCI_SYS_INT_PENDING_CLEAR_ALL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCI_SYS_INT_PENDING_CLEAR_PIO 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCI_SYS_INT_PENDING_CLEAR_DMA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PCI_SYS_INT_PENDING_CLEAR_PCI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCI_IOTLB_CONTROL 0x84 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PCI_INT_SELECT_LO 0x88 /* 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCI_ARBITRATION_SELECT 0x8a /* 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCI_INT_SELECT_HI 0x8c /* 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCI_HW_INT_OUTPUT 0x8e /* 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCI_IOTLB_RAM_INPUT 0x90 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCI_IOTLB_CAM_INPUT 0x94 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PCI_IOTLB_RAM_OUTPUT 0x98 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCI_IOTLB_CAM_OUTPUT 0x9c /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PCI_SMBAR0 0xa0 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PCI_MSIZE0 0xa1 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PCI_PMBAR0 0xa2 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PCI_SMBAR1 0xa4 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PCI_MSIZE1 0xa5 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PCI_PMBAR1 0xa6 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PCI_SIBAR 0xa8 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PCI_SIBAR_ADDRESS_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PCI_ISIZE 0xa9 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PCI_ISIZE_16M 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCI_ISIZE_32M 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PCI_ISIZE_64M 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PCI_ISIZE_128M 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCI_ISIZE_256M 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCI_PIBAR 0xaa /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PCI_CPU_COUNTER_LIMIT_HI 0xac /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PCI_CPU_COUNTER_LIMIT_LO 0xb0 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCI_CPU_COUNTER_LIMIT 0xb4 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCI_SYS_LIMIT 0xb8 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PCI_SYS_COUNTER 0xbc /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PCI_SYS_COUNTER_OVERFLOW (1<<31) /* Limit reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PCI_SYS_LIMIT_PSEUDO 0xc0 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCI_USER_TIMER_CONTROL 0xc4 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCI_USER_TIMER_CONFIG 0xc5 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCI_COUNTER_IRQ 0xc6 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCI_COUNTER_IRQ_SET(sys_irq, cpu_irq) ((((sys_irq) & 0xf) << 4) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ((cpu_irq) & 0xf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCI_COUNTER_IRQ_SYS(v) (((v) >> 4) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCI_COUNTER_IRQ_CPU(v) ((v) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PCI_PIO_ERROR_COMMAND 0xc7 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PCI_PIO_ERROR_ADDRESS 0xc8 /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PCI_IOTLB_ERROR_ADDRESS 0xcc /* 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PCI_SYS_STATUS 0xd0 /* 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCI_SYS_STATUS_RESET_ENABLE (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCI_SYS_STATUS_RESET (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PCI_SYS_STATUS_WATCHDOG_RESET (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PCI_SYS_STATUS_PCI_RESET (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCI_SYS_STATUS_PCI_RESET_ENABLE (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PCI_SYS_STATUS_PCI_SATTELITE_MODE (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #endif /* !(__SPARC_PCIC_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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