^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * obio.h: Some useful locations in 0xFXXXXXXXX PA obio space on sun4d.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SPARC_OBIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SPARC_OBIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/asi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* This weird monster likes to use the very upper parts of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 36bit PA for these things :) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* CSR space (for each XDBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * ------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * | 0xFE | DEVID | | XDBUS ID | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * ------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 35 28 27 20 19 10 9 8 7 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CSR_BASE_ADDR 0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CSR_CPU_SHIFT (32 - 4 - 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CSR_XDBUS_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CSR_BASE(cpu) (((CSR_BASE_ADDR >> CSR_CPU_SHIFT) + cpu) << CSR_CPU_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* ECSR space (not for each XDBUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * ------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * | 0xF | DEVID[7:1] | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * ------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 35 32 31 25 24 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ECSR_BASE_ADDR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ECSR_CPU_SHIFT (32 - 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ECSR_DEV_SHIFT (32 - 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ECSR_BASE(cpu) ((cpu) << ECSR_CPU_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ECSR_DEV_BASE(devid) ((devid) << ECSR_DEV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Bus Watcher */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BW_LOCAL_BASE 0xfff00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BW_CID 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BW_DBUS_CTRL 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BW_DBUS_DATA 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BW_CTRL 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BW_INTR_TABLE 0x00001040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BW_INTR_TABLE_CLEAR 0x00001080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BW_PRESCALER 0x000010c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BW_PTIMER_LIMIT 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BW_PTIMER_COUNTER2 0x00002004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BW_PTIMER_NDLIMIT 0x00002008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BW_PTIMER_CTRL 0x0000200c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BW_PTIMER_COUNTER 0x00002010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BW_TIMER_LIMIT 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BW_TIMER_COUNTER2 0x00003004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BW_TIMER_NDLIMIT 0x00003008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BW_TIMER_CTRL 0x0000300c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BW_TIMER_COUNTER 0x00003010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* BW Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BW_CTRL_USER_TIMER 0x00000004 /* Is User Timer Free run enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Boot Bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BB_LOCAL_BASE 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BB_STAT1 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BB_STAT2 0x00120000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BB_STAT3 0x00140000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BB_LEDS 0x002e0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Bits in BB_STAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BB_STAT2_AC_INTR 0x04 /* Aiee! 5ms and power is gone... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BB_STAT2_TMP_INTR 0x10 /* My Penguins are burning. Are you able to smell it? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BB_STAT2_FAN_INTR 0x20 /* My fan refuses to work */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BB_STAT2_PWR_INTR 0x40 /* On SC2000, one of the two ACs died. Ok, we go on... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BB_STAT2_MASK (BB_STAT2_AC_INTR|BB_STAT2_TMP_INTR|BB_STAT2_FAN_INTR|BB_STAT2_PWR_INTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Cache Controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CC_BASE 0x1F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CC_DATSTREAM 0x1F00000 /* Data stream register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CC_DATSIZE 0x1F0003F /* Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CC_SRCSTREAM 0x1F00100 /* Source stream register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CC_DESSTREAM 0x1F00200 /* Destination stream register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CC_RMCOUNT 0x1F00300 /* Count of references and misses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CC_IPEN 0x1F00406 /* Pending Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CC_IMSK 0x1F00506 /* Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CC_ICLR 0x1F00606 /* Clear pending Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CC_IGEN 0x1F00704 /* Generate Interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CC_STEST 0x1F00804 /* Internal self-test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CC_CREG 0x1F00A04 /* Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CC_SREG 0x1F00B00 /* Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CC_RREG 0x1F00C04 /* Reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CC_EREG 0x1F00E00 /* Error code register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CC_CID 0x1F00F04 /* Component ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline int bw_get_intr_mask(int sbus_level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __asm__ __volatile__ ("lduha [%1] %2, %0" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "=r" (mask) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "r" (BW_LOCAL_BASE + BW_INTR_TABLE + (sbus_level << 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "i" (ASI_M_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline void bw_clear_intr_mask(int sbus_level, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __asm__ __volatile__ ("stha %0, [%1] %2" : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "r" (mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "r" (BW_LOCAL_BASE + BW_INTR_TABLE_CLEAR + (sbus_level << 3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "i" (ASI_M_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static inline unsigned int bw_get_prof_limit(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __asm__ __volatile__ ("lda [%1] %2, %0" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) "=r" (limit) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "i" (ASI_M_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline void bw_set_prof_limit(int cpu, unsigned int limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __asm__ __volatile__ ("sta %0, [%1] %2" : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "r" (limit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "r" (CSR_BASE(cpu) + BW_PTIMER_LIMIT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "i" (ASI_M_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline unsigned int bw_get_ctrl(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __asm__ __volatile__ ("lda [%1] %2, %0" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "=r" (ctrl) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "r" (CSR_BASE(cpu) + BW_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "i" (ASI_M_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline void bw_set_ctrl(int cpu, unsigned int ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __asm__ __volatile__ ("sta %0, [%1] %2" : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "r" (ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "r" (CSR_BASE(cpu) + BW_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "i" (ASI_M_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static inline unsigned int cc_get_ipen(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) __asm__ __volatile__ ("lduha [%1] %2, %0" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "=r" (pending) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "r" (CC_IPEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "i" (ASI_M_MXCC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline void cc_set_iclr(unsigned int clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __asm__ __volatile__ ("stha %0, [%1] %2" : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "r" (clear),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "r" (CC_ICLR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "i" (ASI_M_MXCC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static inline unsigned int cc_get_imsk(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __asm__ __volatile__ ("lduha [%1] %2, %0" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "=r" (mask) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "r" (CC_IMSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "i" (ASI_M_MXCC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static inline void cc_set_imsk(unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) __asm__ __volatile__ ("stha %0, [%1] %2" : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "r" (mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "r" (CC_IMSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "i" (ASI_M_MXCC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline unsigned int cc_get_imsk_other(int cpuid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) __asm__ __volatile__ ("lduha [%1] %2, %0" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "=r" (mask) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "r" (ECSR_BASE(cpuid) | CC_IMSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "i" (ASI_M_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static inline void cc_set_imsk_other(int cpuid, unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) __asm__ __volatile__ ("stha %0, [%1] %2" : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "r" (mask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "r" (ECSR_BASE(cpuid) | CC_IMSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "i" (ASI_M_CTL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static inline void cc_set_igen(unsigned int gen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) __asm__ __volatile__ ("sta %0, [%1] %2" : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "r" (gen),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "r" (CC_IGEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "i" (ASI_M_MXCC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #endif /* !(_SPARC_OBIO_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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