^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* ns87303.h: Configuration Register Description for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * National Semiconductor PC87303 (SuperIO).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SPARC_NS87303_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SPARC_NS87303_H 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Control Register Index Values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define FER 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define FAR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PTR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define FCR 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define KRR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PMC 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TUP 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SID 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ASC 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CS0CF0 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CS0CF1 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CS1CF0 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CS1CF1 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Function Enable Register (FER) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FER_EDM 0x10 /* Encoded Drive and Motor pin information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Function Address Register (FAR) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FAR_LPT_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FAR_LPTB 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FAR_LPTA 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FAR_LPTC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Power and Test Register (PTR) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PTR_LPTB_IRQ7 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PTR_LEVEL_IRQ 0x80 /* When not ECP/EPP: Use level IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controls direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* of the parallel port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Function Control Register (FCR) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FCR_LDE 0x10 /* Logical Drive Exchange */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FCR_ZWS_ENA 0x20 /* Enable short host read/write in ECP/EPP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Printer Control Register (PCR) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCR_EPP_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCR_EPP_IEEE 0x02 /* Enable EPP Version 1.9 (IEEE 1284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCR_ECP_ENABLE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCR_ECP_CLK_ENA 0x08 /* If 0 ECP Clock is stopped on Power down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCR_IRQ_POLAR 0x20 /* If 0 IRQ is level high or negative pulse, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* if 1 polarity is inverted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCR_IRQ_ODRAIN 0x40 /* If 1, IRQ is open drain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Tape UARTs and Parallel Port Config Register (TUP) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TUP_EPP_TIMO 0x02 /* Enable EPP timeout IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Advanced SuperIO Config Register (ASC) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ASC_LPT_IRQ7 0x01 /* Always use IRQ7 for LPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ASC_DRV2_SEL 0x02 /* Logical Drive Exchange controlled by TDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define FER_RESERVED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FAR_RESERVED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PTR_RESERVED 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FCR_RESERVED 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCR_RESERVED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define KRR_RESERVED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PMC_RESERVED 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TUP_RESERVED 0xfb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SIP_RESERVED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ASC_RESERVED 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CS0CF0_RESERVED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CS0CF1_RESERVED 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CS1CF0_RESERVED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CS1CF1_RESERVED 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) extern spinlock_t ns87303_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static inline int ns87303_modify(unsigned long port, unsigned int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned char clr, unsigned char set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static unsigned char reserved[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FER_RESERVED, FAR_RESERVED, PTR_RESERVED, FCR_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PCR_RESERVED, KRR_RESERVED, PMC_RESERVED, TUP_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) SIP_RESERVED, ASC_RESERVED, CS0CF0_RESERVED, CS0CF1_RESERVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) CS1CF0_RESERVED, CS1CF1_RESERVED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned char value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (index > 0x0d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) spin_lock_irqsave(&ns87303_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) outb(index, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) value = inb(port + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) value &= ~(reserved[index] | clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) value |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) outb(value, port + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) outb(value, port + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) spin_unlock_irqrestore(&ns87303_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif /* !(_SPARC_NS87303_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags