^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mxcc.h: Definitions of the Viking MXCC registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SPARC_MXCC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SPARC_MXCC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* These registers are accessed through ASI 0x2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MXCC_DATSTREAM 0x1C00000 /* Data stream register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MXCC_SRCSTREAM 0x1C00100 /* Source stream register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MXCC_DESSTREAM 0x1C00200 /* Destination stream register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MXCC_RMCOUNT 0x1C00300 /* Count of references and misses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MXCC_STEST 0x1C00804 /* Internal self-test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MXCC_CREG 0x1C00A04 /* Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MXCC_SREG 0x1C00B00 /* Status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MXCC_RREG 0x1C00C04 /* Reset register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MXCC_EREG 0x1C00E00 /* Error code register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MXCC_PREG 0x1C00F04 /* Address port register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Some MXCC constants. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MXCC_STREAM_SIZE 0x20 /* Size in bytes of one stream r/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* The MXCC Control Register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * | | RRC | RSV |PRE|MCE|PARE|ECE|RSV|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * ----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 31 10 9 8-6 5 4 3 2 1-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * RRC: Controls what you read from MXCC_RMCOUNT reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * 0=Misses 1=References
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * PRE: Prefetch enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * MCE: Multiple Command Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * PARE: Parity enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * ECE: External cache enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MXCC_CTL_RRC 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MXCC_CTL_PRE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MXCC_CTL_MCE 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MXCC_CTL_PARE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MXCC_CTL_ECE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* The MXCC Error Register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * |ME| RSV|CE|PEW|PEE|ASE|EIV| MOPC|ECODE|PRIV|RSV|HPADDR|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * --------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 31 30 29 28 27 26 25 24-15 14-7 6 5-3 2-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * ME: Multiple Errors have occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * CE: Cache consistency Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * PEW: Parity Error during a Write operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * PEE: Parity Error involving the External cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * ASE: ASynchronous Error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * EIV: This register is toast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * MOPC: MXCC Operation Code for instance causing error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * ECODE: The Error CODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * PRIV: A privileged mode error? 0=no 1=yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * HPADDR: High PhysicalADDRess bits (35-32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MXCC_ERR_ME 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MXCC_ERR_CE 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MXCC_ERR_PEW 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MXCC_ERR_PEE 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MXCC_ERR_ASE 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MXCC_ERR_EIV 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MXCC_ERR_MOPC 0x01FF8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MXCC_ERR_ECODE 0x00007F80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MXCC_ERR_PRIV 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MXCC_ERR_HPADDR 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* The MXCC Port register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * -----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * | | MID | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * -----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * 31 21 20-18 17 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * MID: The moduleID of the cpu your read this from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static inline void mxcc_set_stream_src(unsigned long *paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long data0 = paddr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long data1 = paddr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) "or %%g0, %1, %%g3\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) "stda %%g2, [%2] %3\n\t" : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "r" (data0), "r" (data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "r" (MXCC_SRCSTREAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "i" (ASI_M_MXCC) : "g2", "g3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static inline void mxcc_set_stream_dst(unsigned long *paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long data0 = paddr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long data1 = paddr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "or %%g0, %1, %%g3\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "stda %%g2, [%2] %3\n\t" : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "r" (data0), "r" (data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "r" (MXCC_DESSTREAM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "i" (ASI_M_MXCC) : "g2", "g3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static inline unsigned long mxcc_get_creg(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned long mxcc_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) __asm__ __volatile__("set 0xffffffff, %%g2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "set 0xffffffff, %%g3\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "stda %%g2, [%1] %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "lda [%3] %2, %0\n\t" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "=r" (mxcc_control) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "r" (MXCC_EREG), "i" (ASI_M_MXCC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "r" (MXCC_CREG) : "g2", "g3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return mxcc_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static inline void mxcc_set_creg(unsigned long mxcc_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "r" (mxcc_control), "r" (MXCC_CREG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "i" (ASI_M_MXCC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #endif /* !(_SPARC_MXCC_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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