^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mbus.h: Various defines for MBUS modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _SPARC_MBUS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _SPARC_MBUS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/ross.h> /* HyperSparc stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/viking.h> /* Ugh, bug city... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum mbus_module {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) HyperSparc = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Swift_ok = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Swift_bad_c = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Swift_lots_o_bugs = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Tsunami = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Viking_12 = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Viking_2x = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Viking_30 = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Viking_35 = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Viking_new = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) TurboSparc = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SRMMU_INVAL_MOD = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) extern enum mbus_module srmmu_modtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) extern unsigned int viking_rev, swift_rev, cypress_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* HW Mbus module bugs we have to deal with */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HWBUG_COPYBACK_BROKEN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HWBUG_ASIFLUSH_BROKEN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HWBUG_VACFLUSH_BITROT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HWBUG_KERN_ACCBROKEN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HWBUG_KERN_CBITBROKEN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HWBUG_MODIFIED_BITROT 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HWBUG_PC_BADFAULT_ADDR 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HWBUG_SUPERSCALAR_BAD 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HWBUG_PACINIT_BITROT 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* First the module type values. To find out which you have, just load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * the mmu control register from ASI_M_MMUREG alternate address space and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * shift the value right 28 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* IMPL field means the company which produced the chip. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MBUS_VIKING 0x4 /* bleech, Texas Instruments Module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MBUS_LSI 0x3 /* LSI Logics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MBUS_ROSS 0x1 /* Ross is nice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MBUS_FMI 0x0 /* Fujitsu Microelectronics/Swift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Ross Module versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ROSS_604_REV_CDE 0x0 /* revisions c, d, and e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ROSS_604_REV_F 0x1 /* revision f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ROSS_605 0xf /* revision a, a.1, and a.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ROSS_605_REV_B 0xe /* revision b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* TI Viking Module versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VIKING_REV_12 0x1 /* Version 1.2 or SPARCclassic's CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VIKING_REV_2 0x2 /* Version 2.1, 2.2, 2.3, and 2.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VIKING_REV_30 0x3 /* Version 3.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define VIKING_REV_35 0x4 /* Version 3.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* LSI Logics. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LSI_L64815 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Fujitsu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FMI_AURORA 0x4 /* MB8690x, a Swift module... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FMI_TURBO 0x5 /* MB86907, a TurboSparc module... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* For multiprocessor support we need to be able to obtain the CPU id and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * the MBUS Module id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* The CPU ID is encoded in the trap base register, 20 bits to the left of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * bit zero, with 2 bits being significant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TBR_ID_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static inline int get_cpuid(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) register int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __asm__ __volatile__("rd %%tbr, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "srl %0, %1, %0\n\t" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "=r" (retval) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) "i" (TBR_ID_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return (retval & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static inline int get_modid(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return (get_cpuid() | 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #endif /* !(_SPARC_MBUS_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags