Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _SPARC64_LSU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _SPARC64_LSU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/const.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) /* LSU Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define LSU_CONTROL_VM _AC(0x00000001fe000000,UL) /* Virt-watchpoint byte mask*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define LSU_CONTROL_PR _AC(0x0000000001000000,UL) /* Phys-rd watchpoint enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define LSU_CONTROL_PW _AC(0x0000000000800000,UL) /* Phys-wr watchpoint enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define LSU_CONTROL_VR _AC(0x0000000000400000,UL) /* Virt-rd watchpoint enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define LSU_CONTROL_VW _AC(0x0000000000200000,UL) /* Virt-wr watchpoint enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define LSU_CONTROL_FM _AC(0x00000000000ffff0,UL) /* Parity mask enables.     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable.         */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define LSU_CONTROL_DC _AC(0x0000000000000002,UL) /* Data cache enable.       */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LSU_CONTROL_IC _AC(0x0000000000000001,UL) /* Instruction cache enable.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #endif /* !(_SPARC64_LSU_H) */