Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* io-unit.h: Definitions for the sun4d IO-UNIT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _SPARC_IO_UNIT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _SPARC_IO_UNIT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* The io-unit handles all virtual to physical address translations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * that occur between the SBUS and physical memory.  Access by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * the cpu to IO registers and similar go over the xdbus so are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * translated by the on chip SRMMU.  The io-unit and the srmmu do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * not need to have the same translations at all, in fact most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * of the time the translations they handle are a disjunct set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * Basically the io-unit handles all dvma sbus activity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* AIEEE, unlike the nice sun4m, these monsters have 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)    fixed DMA range 64M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IOUNIT_DMA_BASE	    0xfc000000 /* TOP - 64M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IOUNIT_DMA_SIZE	    0x04000000 /* 64M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* We use last 1M for sparc_dvma_malloc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IOUNIT_DVMA_SIZE    0x00100000 /* 1M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* The format of an iopte in the external page tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IOUPTE_PAGE          0xffffff00 /* Physical page number (PA[35:12])	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IOUPTE_CACHE         0x00000080 /* Cached (in Viking/MXCC)		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* XXX Jakub, find out how to program SBUS streaming cache on XDBUS/sun4d.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * XXX Actually, all you should need to do is find out where the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * XXX are and copy over the sparc64 implementation I wrote.  There may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * XXX some horrible hwbugs though, so be careful.  -DaveM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IOUPTE_STREAM        0x00000040 /* Translation can use streaming cache	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IOUPTE_INTRA	     0x00000008 /* SBUS direct slot->slot transfer	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IOUPTE_WRITE         0x00000004 /* Writeable				*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IOUPTE_VALID         0x00000002 /* IOPTE is valid			*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IOUPTE_PARITY        0x00000001 /* Parity is checked during DVMA	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct iounit_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	unsigned long		bmap[(IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 3)) / sizeof(unsigned long)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	spinlock_t		lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	iopte_t __iomem		*page_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	unsigned long		rotor[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	unsigned long		limit[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IOUNIT_BMAP1_START	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IOUNIT_BMAP1_END	(IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IOUNIT_BMAP2_START	IOUNIT_BMAP1_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IOUNIT_BMAP2_END	IOUNIT_BMAP2_START + (IOUNIT_DMA_SIZE >> (PAGE_SHIFT + 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IOUNIT_BMAPM_START	IOUNIT_BMAP2_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IOUNIT_BMAPM_END	((IOUNIT_DMA_SIZE - IOUNIT_DVMA_SIZE) >> PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif /* !(_SPARC_IO_UNIT_H) */