^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* ide.h: SPARC PCI specific IDE glue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 1997 David S. Miller (davem@davemloft.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Adaptation from sparc64 version to sparc by Pete Zaitcev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _SPARC_IDE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _SPARC_IDE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifdef CONFIG_SPARC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/spitfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/psr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define __ide_insl(data_reg, buffer, wcount) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) __ide_insw(data_reg, buffer, (wcount)<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define __ide_outsl(data_reg, buffer, wcount) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) __ide_outsw(data_reg, buffer, (wcount)<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* On sparc, I/O ports and MMIO registers are accessed identically. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define __ide_mm_insw __ide_insw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define __ide_mm_insl __ide_insl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define __ide_mm_outsw __ide_outsw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define __ide_mm_outsl __ide_outsl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static inline void __ide_insw(void __iomem *port, void *dst, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long end = (unsigned long)dst + (count << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u16 *ps = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 *pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if(((unsigned long)ps) & 0x2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *ps++ = __raw_readw(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) pi = (u32 *)ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) while(count >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) w = __raw_readw(port) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) w |= __raw_readw(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *pi++ = w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) count -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ps = (u16 *)pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if(count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *ps++ = __raw_readw(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __flush_dcache_range((unsigned long)dst, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static inline void __ide_outsw(void __iomem *port, const void *src, u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned long end = (unsigned long)src + (count << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const u16 *ps = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) const u32 *pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if(((unsigned long)src) & 0x2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __raw_writew(*ps++, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pi = (const u32 *)ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) while(count >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) w = *pi++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __raw_writew((w >> 16), port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __raw_writew(w, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) count -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ps = (const u16 *)pi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if(count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __raw_writew(*ps, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #if defined(CONFIG_SPARC64) && defined(DCACHE_ALIASING_POSSIBLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __flush_dcache_range((unsigned long)src, end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #endif /* _SPARC_IDE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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