^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _SPARC64_ESTATE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _SPARC64_ESTATE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* UltraSPARC-III E-cache Error Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define ESTATE_ERROR_FMT 0x0000000000040000 /* Force MTAG ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define ESTATE_ERROR_FMESS 0x000000000003c000 /* Forced MTAG ECC val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define ESTATE_ERROR_FMD 0x0000000000002000 /* Force DATA ECC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define ESTATE_ERROR_FDECC 0x0000000000001ff0 /* Forced DATA ECC val */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ESTATE_ERROR_UCEEN 0x0000000000000008 /* See below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ESTATE_ERROR_NCEEN 0x0000000000000002 /* See below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ESTATE_ERROR_CEEN 0x0000000000000001 /* See below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* UCEEN enables the fast_ECC_error trap for: 1) software correctable E-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * errors 2) uncorrectable E-cache errors. Such events only occur on reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * of the E-cache by the local processor for: 1) data loads 2) instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * fetches 3) atomic operations. Such events _cannot_ occur for: 1) merge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 2) writeback 2) copyout. The AFSR bits associated with these traps are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * UCC and UCU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* NCEEN enables instruction_access_error, data_access_error, and ECC_error traps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * for uncorrectable ECC errors and system errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Uncorrectable system bus data error or MTAG ECC error, system bus TimeOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * or system bus BusERR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * 1) As the result of an instruction fetch, will generate instruction_access_error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * 2) As the result of a load etc. will generate data_access_error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * 3) As the result of store merge completion, writeback, or copyout will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * generate a disrupting ECC_error trap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 4) As the result of such errors on instruction vector fetch can generate any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * of the 3 trap types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * The AFSR bits associated with these traps are EMU, EDU, WDU, CPU, IVU, UE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * BERR, and TO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* CEEN enables the ECC_error trap for hardware corrected ECC errors. System bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * reads resulting in a hardware corrected data or MTAG ECC error will generate an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * ECC_error disrupting trap with this bit enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * This same trap will also be generated when a hardware corrected ECC error results
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * during store merge, writeback, and copyout operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* In general, if the trap enable bits above are disabled the AFSR bits will still
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * log the events even though the trap will not be generated by the processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif /* _SPARC64_ESTATE_H */