^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ecc.h: Definitions and defines for the external cache/memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * controller on the sun4m.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _SPARC_ECC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _SPARC_ECC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* These registers are accessed through the SRMMU passthrough ASI 0x20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ECC_ENABLE 0x00000000 /* ECC enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ECC_FSTATUS 0x00000008 /* ECC fault status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ECC_FADDR 0x00000010 /* ECC fault address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ECC_DIGNOSTIC 0x00000018 /* ECC diagnostics register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ECC_MBAENAB 0x00000020 /* MBus arbiter enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ECC_DMESG 0x00001000 /* Diagnostic message passing area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* ECC MBus Arbiter Enable register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * ----------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * | |SBUS|MOD3|MOD2|MOD1|RSV|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * ----------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 31 5 4 3 2 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * MOD3: Enable MBus Arbiter on MBus module 3 0=off 1=on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * MOD2: Enable MBus Arbiter on MBus module 2 0=off 1=on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * MOD1: Enable MBus Arbiter on MBus module 1 0=off 1=on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ECC_MBAE_SBUS 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ECC_MBAE_MOD3 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ECC_MBAE_MOD2 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ECC_MBAE_MOD1 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* ECC Fault Control Register layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * -----------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * | RESV | ECHECK | EINT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * -----------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 31 2 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * ECHECK: Enable ECC checking. 0=off 1=on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * EINT: Enable Interrupts for correctable errors. 0=off 1=on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ECC_FCR_CHECK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ECC_FCR_INTENAB 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* ECC Fault Address Register Zero layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * -----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * | MID | S | RSV | VA | BM |AT| C| SZ |TYP| PADDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * -----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 31-28 27 26-22 21-14 13 12 11 10-8 7-4 3-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * MID: ModuleID of the faulting processor. ie. who did it?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * S: Supervisor/Privileged access? 0=no 1=yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * VA: Bits 19-12 of the virtual faulting address, these are the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * superset bits in the virtual cache and can be used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * a flush operation if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * BM: Boot mode? 0=no 1=yes This is just like the SRMMU boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * mode bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * AT: Did this fault happen during an atomic instruction? 0=no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * 1=yes. This means either an 'ldstub' or 'swap' instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * was in progress (but not finished) when this fault happened.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * This indicated whether the bus was locked when the fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * occurred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * C: Did the pte for this access indicate that it was cacheable?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * 0=no 1=yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * SZ: The size of the transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * TYP: The transaction type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * PADDR: Bits 35-32 of the physical address for the fault.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ECC_FADDR0_MIDMASK 0xf0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ECC_FADDR0_S 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ECC_FADDR0_VADDR 0x003fc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ECC_FADDR0_BMODE 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ECC_FADDR0_ATOMIC 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ECC_FADDR0_CACHE 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ECC_FADDR0_SIZE 0x00000700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ECC_FADDR0_TYPE 0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ECC_FADDR0_PADDR 0x0000000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* ECC Fault Address Register One layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * -------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * | Physical Address 31-0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * -------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * 31 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * You get the upper 4 bits of the physical address from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * PADDR field in ECC Fault Address Zero register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* ECC Fault Status Register layout:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * ----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * | RESV|C2E|MULT|SYNDROME|DWORD|UNC|TIMEO|BS|C|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * ----------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * 31-18 17 16 15-8 7-4 3 2 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * MULT: Multiple errors occurred ;-O 0=no 1=prom_panic(yes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * SYNDROME: Controller is mentally unstable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * DWORD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * UNC: Uncorrectable error. 0=no 1=yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * TIMEO: Timeout occurred. 0=no 1=yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * C: Correctable error? 0=no 1=yes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ECC_FSR_C2ERR 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ECC_FSR_MULT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ECC_FSR_SYND 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ECC_FSR_DWORD 0x000000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ECC_FSR_UNC 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ECC_FSR_TIMEO 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ECC_FSR_BADSLOT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ECC_FSR_C 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #endif /* !(_SPARC_ECC_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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