^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_SPARC_DMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_SPARC_DMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* These are irrelevant for Sparc DMA, but we leave it in so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * things can compile.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define MAX_DMA_CHANNELS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define DMA_MODE_READ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DMA_MODE_WRITE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MAX_DMA_ADDRESS (~0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Useful constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SIZE_16MB (16*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SIZE_64K (64*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* SBUS DMA controller reg offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Fields in the cond_reg register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* First, the version identification bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DMA_VERS0 0x00000000 /* Sunray DMA version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DMA_VERS1 0x80000000 /* DMA rev 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DMA_VERS2 0xa0000000 /* DMA rev 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DMA_VERHME 0xb0000000 /* DMA hme gate array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DMA_ST_WRITE 0x00000100 /* write from device to memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DMA_BRST64 0x000c0000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Values describing the burst-size property from the PROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DMA_BURST1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DMA_BURST2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DMA_BURST4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DMA_BURST8 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DMA_BURST16 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DMA_BURST32 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DMA_BURST64 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DMA_BURSTBITS 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* From PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) extern int isa_dma_bridge_buggy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define isa_dma_bridge_buggy (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #ifdef CONFIG_SPARC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned long sparc_dma_alloc_resource(struct device *dev, size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) bool sparc_dma_free_resource(void *cpu_addr, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif /* !(_ASM_SPARC_DMA_H) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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