Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _SPARC64_DCU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _SPARC64_DCU_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/const.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) /* UltraSparc-III Data Cache Unit Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define DCU_CP	_AC(0x0002000000000000,UL) /* Phys Cache Enable w/o mmu	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define DCU_CV	_AC(0x0001000000000000,UL) /* Virt Cache Enable w/o mmu	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DCU_ME	_AC(0x0000800000000000,UL) /* NC-store Merging Enable	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DCU_RE	_AC(0x0000400000000000,UL) /* RAW bypass Enable		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DCU_PE	_AC(0x0000200000000000,UL) /* PCache Enable		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DCU_HPE	_AC(0x0000100000000000,UL) /* HW prefetch Enable	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DCU_SPE	_AC(0x0000080000000000,UL) /* SW prefetch Enable	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DCU_SL	_AC(0x0000040000000000,UL) /* Secondary ld-steering Enab*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DCU_WE	_AC(0x0000020000000000,UL) /* WCache enable		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DCU_PM	_AC(0x000001fe00000000,UL) /* PA Watchpoint Byte Mask	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DCU_VM	_AC(0x00000001fe000000,UL) /* VA Watchpoint Byte Mask	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DCU_PR	_AC(0x0000000001000000,UL) /* PA Watchpoint Read Enable	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DCU_PW	_AC(0x0000000000800000,UL) /* PA Watchpoint Write Enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DCU_VR	_AC(0x0000000000400000,UL) /* VA Watchpoint Read Enable	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DCU_VW	_AC(0x0000000000200000,UL) /* VA Watchpoint Write Enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DCU_DM	_AC(0x0000000000000008,UL) /* DMMU Enable		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DCU_IM	_AC(0x0000000000000004,UL) /* IMMU Enable		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DCU_DC	_AC(0x0000000000000002,UL) /* Data Cache Enable		*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DCU_IC	_AC(0x0000000000000001,UL) /* Instruction Cache Enable	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif /* _SPARC64_DCU_H */