^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _SPARC64_CHMCTRL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _SPARC64_CHMCTRL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* Cheetah memory controller programmable registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define CHMCTRL_TCTRL1 0x00 /* Memory Timing Control I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define CHMCTRL_TCTRL2 0x08 /* Memory Timing Control II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define CHMCTRL_TCTRL3 0x38 /* Memory Timing Control III */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CHMCTRL_TCTRL4 0x40 /* Memory Timing Control IV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CHMCTRL_DECODE1 0x10 /* Memory Address Decode I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CHMCTRL_DECODE2 0x18 /* Memory Address Decode II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CHMCTRL_DECODE3 0x20 /* Memory Address Decode III */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CHMCTRL_DECODE4 0x28 /* Memory Address Decode IV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CHMCTRL_MACTRL 0x30 /* Memory Address Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Memory Timing Control I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TCTRL1_SDRAMCTL_DLY 0xf000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TCTRL1_SDRAMCTL_DLY_SHIFT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TCTRL1_SDRAMCLK_DLY 0x0e00000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TCTRL1_SDRAMCLK_DLY_SHIFT 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TCTRL1_R 0x0100000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TCTRL1_R_SHIFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TCTRL1_AUTORFR_CYCLE 0x00fe000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TCTRL1_AUTORFR_CYCLE_SHIFT 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TCTRL1_RD_WAIT 0x0001f00000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TCTRL1_RD_WAIT_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TCTRL1_PC_CYCLE 0x00000fc000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TCTRL1_PC_CYCLE_SHIFT 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TCTRL1_WR_MORE_RAS_PW 0x0000003f00000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TCTRL1_WR_MORE_RAS_PW_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TCTRL1_RD_MORE_RAW_PW 0x00000000fc000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TCTRL1_RD_MORE_RAS_PW_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TCTRL1_ACT_WR_DLY 0x0000000003f00000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TCTRL1_ACT_WR_DLY_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TCTRL1_ACT_RD_DLY 0x00000000000fc000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TCTRL1_ACT_RD_DLY_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TCTRL1_BANK_PRESENT 0x0000000000003000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TCTRL1_BANK_PRESENT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TCTRL1_RFR_INT 0x0000000000000ff8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TCTRL1_RFR_INT_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TCTRL1_SET_MODE_REG 0x0000000000000004UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TCTRL1_SET_MODE_REG_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TCTRL1_RFR_ENABLE 0x0000000000000002UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TCTRL1_RFR_ENABLE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TCTRL1_PRECHG_ALL 0x0000000000000001UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TCTRL1_PRECHG_ALL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Memory Timing Control II */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TCTRL2_WR_MSEL_DLY 0xfc00000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TCTRL2_WR_MSEL_DLY_SHIFT 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TCTRL2_RD_MSEL_DLY 0x03f0000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TCTRL2_RD_MSEL_DLY_SHIFT 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TCTRL2_WRDATA_THLD 0x000c000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TCTRL2_WRDATA_THLD_SHIFT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TCTRL2_RDWR_RD_TI_DLY 0x0003f00000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TCTRL2_RDWR_RD_TI_DLY_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TCTRL2_AUTOPRECHG_ENBL 0x0000080000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TCTRL2_AUTOPRECHG_ENBL_SHIFT 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TCTRL2_RDWR_PI_MORE_DLY 0x000007c000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TCTRL2_RDWR_PI_MORE_DLY_SHIFT 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TCTRL2_RDWR_1_DLY 0x0000003f00000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TCTRL2_RDWR_1_DLY_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TCTRL2_WRWR_PI_MORE_DLY 0x00000000f8000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TCTRL2_WRWR_PI_MORE_DLY_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TCTRL2_WRWR_1_DLY 0x0000000007e00000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TCTRL2_WRWR_1_DLY_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TCTRL2_RDWR_RD_PI_MORE_DLY 0x00000000001f0000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TCTRL2_RDWR_RD_PI_MORE_DLY_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TCTRL2_R 0x0000000000008000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TCTRL2_R_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TCTRL2_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TCTRL2_SDRAM_MODE_REG_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Memory Timing Control III */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TCTRL3_SDRAM_CTL_DLY 0xf000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TCTRL3_SDRAM_CTL_DLY_SHIFT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TCTRL3_SDRAM_CLK_DLY 0x0e00000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TCTRL3_SDRAM_CLK_DLY_SHIFT 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TCTRL3_R 0x0100000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TCTRL3_R_SHIFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TCTRL3_AUTO_RFR_CYCLE 0x00fe000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TCTRL3_AUTO_RFR_CYCLE_SHIFT 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TCTRL3_RD_WAIT 0x0001f00000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TCTRL3_RD_WAIT_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TCTRL3_PC_CYCLE 0x00000fc000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TCTRL3_PC_CYCLE_SHIFT 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TCTRL3_WR_MORE_RAW_PW 0x0000003f00000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TCTRL3_WR_MORE_RAW_PW_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TCTRL3_RD_MORE_RAW_PW 0x00000000fc000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TCTRL3_RD_MORE_RAW_PW_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TCTRL3_ACT_WR_DLY 0x0000000003f00000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TCTRL3_ACT_WR_DLY_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TCTRL3_ACT_RD_DLY 0x00000000000fc000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TCTRL3_ACT_RD_DLY_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TCTRL3_BANK_PRESENT 0x0000000000003000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TCTRL3_BANK_PRESENT_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TCTRL3_RFR_INT 0x0000000000000ff8UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TCTRL3_RFR_INT_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TCTRL3_SET_MODE_REG 0x0000000000000004UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TCTRL3_SET_MODE_REG_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TCTRL3_RFR_ENABLE 0x0000000000000002UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TCTRL3_RFR_ENABLE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TCTRL3_PRECHG_ALL 0x0000000000000001UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TCTRL3_PRECHG_ALL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Memory Timing Control IV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TCTRL4_WR_MSEL_DLY 0xfc00000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TCTRL4_WR_MSEL_DLY_SHIFT 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TCTRL4_RD_MSEL_DLY 0x03f0000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TCTRL4_RD_MSEL_DLY_SHIFT 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TCTRL4_WRDATA_THLD 0x000c000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TCTRL4_WRDATA_THLD_SHIFT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TCTRL4_RDWR_RD_RI_DLY 0x0003f00000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TCTRL4_RDWR_RD_RI_DLY_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TCTRL4_AUTO_PRECHG_ENBL 0x0000080000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TCTRL4_AUTO_PRECHG_ENBL_SHIFT 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TCTRL4_RD_WR_PI_MORE_DLY 0x000007c000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TCTRL4_RD_WR_PI_MORE_DLY_SHIFT 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TCTRL4_RD_WR_TI_DLY 0x0000003f00000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TCTRL4_RD_WR_TI_DLY_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TCTRL4_WR_WR_PI_MORE_DLY 0x00000000f8000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TCTRL4_WR_WR_PI_MORE_DLY_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TCTRL4_WR_WR_TI_DLY 0x0000000007e00000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TCTRL4_WR_WR_TI_DLY_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TCTRL4_RDWR_RD_PI_MORE_DLY 0x00000000001f000UL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TCTRL4_RDWR_RD_PI_MORE_DLY_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TCTRL4_R 0x0000000000008000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TCTRL4_R_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TCTRL4_SDRAM_MODE_REG_DATA 0x0000000000007fffUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TCTRL4_SDRAM_MODE_REG_DATA_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* All 4 memory address decoding registers have the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * same layout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MEM_DECODE_VALID 0x8000000000000000UL /* Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MEM_DECODE_VALID_SHIFT 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MEM_DECODE_UK 0x001ffe0000000000UL /* Upper mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MEM_DECODE_UK_SHIFT 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MEM_DECODE_UM 0x0000001ffff00000UL /* Upper match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MEM_DECODE_UM_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MEM_DECODE_LK 0x000000000003c000UL /* Lower mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MEM_DECODE_LK_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MEM_DECODE_LM 0x0000000000000f00UL /* Lower match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MEM_DECODE_LM_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PA_UPPER_BITS 0x000007fffc000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PA_UPPER_BITS_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PA_LOWER_BITS 0x00000000000003c0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PA_LOWER_BITS_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MACTRL_R0 0x8000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MACTRL_R0_SHIFT 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MACTRL_ADDR_LE_PW 0x7000000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MACTRL_ADDR_LE_PW_SHIFT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MACTRL_CMD_PW 0x0f00000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MACTRL_CMD_PW_SHIFT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MACTRL_HALF_MODE_WR_MSEL_DLY 0x00fc000000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MACTRL_HALF_MODE_WR_MSEL_DLY_SHIFT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MACTRL_HALF_MODE_RD_MSEL_DLY 0x0003f00000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MACTRL_HALF_MODE_RD_MSEL_DLY_SHIFT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MACTRL_HALF_MODE_SDRAM_CTL_DLY 0x00000f0000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MACTRL_HALF_MODE_SDRAM_CTL_DLY_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MACTRL_HALF_MODE_SDRAM_CLK_DLY 0x000000e000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MACTRL_HALF_MODE_SDRAM_CLK_DLY_SHIFT 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MACTRL_R1 0x0000001000000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MACTRL_R1_SHIFT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3 0x0000000f00000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B3_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MACTRL_ENC_INTLV_B3 0x00000000f8000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MACTRL_ENC_INTLV_B3_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2 0x0000000007800000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B2_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MACTRL_ENC_INTLV_B2 0x00000000007c0000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MACTRL_ENC_INTLV_B2_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1 0x000000000003c000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B1_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MACTRL_ENC_INTLV_B1 0x0000000000003e00UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MACTRL_ENC_INTLV_B1_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0 0x00000000000001e0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MACTRL_BANKSEL_N_ROWADDR_SIZE_B0_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MACTRL_ENC_INTLV_B0 0x000000000000001fUL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MACTRL_ENC_INTLV_B0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif /* _SPARC64_CHMCTRL_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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