Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef _SPARC64_CHAFSR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define _SPARC64_CHAFSR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) /* Cheetah Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) /* Comments indicate which processor variants on which the bit definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * is valid.  Codes are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * ch	-->	cheetah
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * ch+	-->	cheetah plus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * jp	-->	jalapeno
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /* All bits of this register except M_SYNDROME and E_SYNDROME are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * read, write 1 to clear.  M_SYNDROME and E_SYNDROME are read-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* Software bit set by linux trap handlers to indicate that the trap was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * signalled at %tl >= 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CHAFSR_TL1		(1UL << 63UL) /* n/a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* Unmapped error from system bus for prefetch queue or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * store queue read operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CHPAFSR_DTO		(1UL << 59UL) /* ch+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* Bus error from system bus for prefetch queue or store queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * read operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CHPAFSR_DBERR		(1UL << 58UL) /* ch+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* Hardware corrected E-cache Tag ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CHPAFSR_THCE		(1UL << 57UL) /* ch+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* System interface protocol error, hw timeout caused */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define JPAFSR_JETO		(1UL << 57UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* SW handled correctable E-cache Tag ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CHPAFSR_TSCE		(1UL << 56UL) /* ch+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* Parity error on system snoop results */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define JPAFSR_SCE		(1UL << 56UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* Uncorrectable E-cache Tag ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CHPAFSR_TUE		(1UL << 55UL) /* ch+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* System interface protocol error, illegal command detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define JPAFSR_JEIC		(1UL << 55UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* Uncorrectable system bus data ECC error due to prefetch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * or store fill request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CHPAFSR_DUE		(1UL << 54UL) /* ch+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /* System interface protocol error, illegal ADTYPE detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define JPAFSR_JEIT		(1UL << 54UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* Multiple errors of the same type have occurred.  This bit is set when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * an uncorrectable error or a SW correctable error occurs and the status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * bit to report that error is already set.  When multiple errors of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * different types are indicated by setting multiple status bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * This bit is not set if multiple HW corrected errors with the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * status bit occur, only uncorrectable and SW correctable ones have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * this behavior.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * This bit is not set when multiple ECC errors happen within a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * 64-byte system bus transaction.  Only the first ECC error in a 16-byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * subunit will be logged.  All errors in subsequent 16-byte subunits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * from the same 64-byte transaction are ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CHAFSR_ME		(1UL << 53UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /* Privileged state error has occurred.  This is a capture of PSTATE.PRIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * at the time the error is detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CHAFSR_PRIV		(1UL << 52UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /* The following bits 51 (CHAFSR_PERR) to 33 (CHAFSR_CE) are sticky error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * bits and record the most recently detected errors.  Bits accumulate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  * errors that have been detected since the last write to clear the bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* System interface protocol error.  The processor asserts its' ERROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  * pin when this event occurs and it also logs a specific cause code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  * into a JTAG scannable flop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CHAFSR_PERR		(1UL << 51UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* Internal processor error.  The processor asserts its' ERROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * pin when this event occurs and it also logs a specific cause code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * into a JTAG scannable flop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CHAFSR_IERR		(1UL << 50UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* System request parity error on incoming address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CHAFSR_ISAP		(1UL << 49UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* HW Corrected system bus MTAG ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CHAFSR_EMC		(1UL << 48UL) /* ch,ch+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /* Parity error on L2 cache tag SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define JPAFSR_ETP		(1UL << 48UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Uncorrectable system bus MTAG ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CHAFSR_EMU		(1UL << 47UL) /* ch,ch+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Out of range memory error has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define JPAFSR_OM		(1UL << 47UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* HW Corrected system bus data ECC error for read of interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CHAFSR_IVC		(1UL << 46UL) /* ch,ch+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Error due to unsupported store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define JPAFSR_UMS		(1UL << 46UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Uncorrectable system bus data ECC error for read of interrupt vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CHAFSR_IVU		(1UL << 45UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Unmapped error from system bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CHAFSR_TO		(1UL << 44UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Bus error response from system bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CHAFSR_BERR		(1UL << 43UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* SW Correctable E-cache ECC error for instruction fetch or data access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * other than block load.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CHAFSR_UCC		(1UL << 42UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Uncorrectable E-cache ECC error for instruction fetch or data access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * other than block load.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CHAFSR_UCU		(1UL << 41UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Copyout HW Corrected ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CHAFSR_CPC		(1UL << 40UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Copyout Uncorrectable ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CHAFSR_CPU		(1UL << 39UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* HW Corrected ECC error from E-cache for writeback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CHAFSR_WDC		(1UL << 38UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Uncorrectable ECC error from E-cache for writeback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CHAFSR_WDU		(1UL << 37UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* HW Corrected ECC error from E-cache for store merge or block load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CHAFSR_EDC		(1UL << 36UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Uncorrectable ECC error from E-cache for store merge or block load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CHAFSR_EDU		(1UL << 35UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Uncorrectable system bus data ECC error for read of memory or I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CHAFSR_UE		(1UL << 34UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* HW Corrected system bus data ECC error for read of memory or I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CHAFSR_CE		(1UL << 33UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Uncorrectable ECC error from remote cache/memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define JPAFSR_RUE		(1UL << 32UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Correctable ECC error from remote cache/memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define JPAFSR_RCE		(1UL << 31UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* JBUS parity error on returned read data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define JPAFSR_BP		(1UL << 30UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* JBUS parity error on data for writeback or block store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define JPAFSR_WBP		(1UL << 29UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Foreign read to DRAM incurring correctable ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define JPAFSR_FRC		(1UL << 28UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Foreign read to DRAM incurring uncorrectable ECC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define JPAFSR_FRU		(1UL << 27UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CHAFSR_ERRORS		(CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CHPAFSR_ERRORS		(CHPAFSR_DTO | CHPAFSR_DBERR | CHPAFSR_THCE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 				 CHPAFSR_TSCE | CHPAFSR_TUE | CHPAFSR_DUE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 				 CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP | CHAFSR_EMC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 				 CHAFSR_EMU | CHAFSR_IVC | CHAFSR_IVU | CHAFSR_TO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 				 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | CHAFSR_CPC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 				 CHAFSR_CPU | CHAFSR_WDC | CHAFSR_WDU | CHAFSR_EDC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 				 CHAFSR_EDU | CHAFSR_UE | CHAFSR_CE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define JPAFSR_ERRORS		(JPAFSR_JETO | JPAFSR_SCE | JPAFSR_JEIC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 				 JPAFSR_JEIT | CHAFSR_PERR | CHAFSR_IERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				 CHAFSR_ISAP | JPAFSR_ETP | JPAFSR_OM | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 				 JPAFSR_UMS | CHAFSR_IVU | CHAFSR_TO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 				 CHAFSR_BERR | CHAFSR_UCC | CHAFSR_UCU | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				 CHAFSR_CPC | CHAFSR_CPU | CHAFSR_WDC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				 CHAFSR_WDU | CHAFSR_EDC | CHAFSR_EDU | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 				 CHAFSR_UE | CHAFSR_CE | JPAFSR_RUE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 				 JPAFSR_RCE | JPAFSR_BP | JPAFSR_WBP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 				 JPAFSR_FRC | JPAFSR_FRU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Active JBUS request signal when error occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define JPAFSR_JBREQ		(0x7UL << 24UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define JPAFSR_JBREQ_SHIFT	24UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* L2 cache way information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define JPAFSR_ETW		(0x3UL << 22UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define JPAFSR_ETW_SHIFT	22UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* System bus MTAG ECC syndrome.  This field captures the status of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  * first occurrence of the highest-priority error according to the M_SYND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * overwrite policy.  After the AFSR sticky bit, corresponding to the error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * for which the M_SYND is reported, is cleared, the contents of the M_SYND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  * field will be unchanged by will be unfrozen for further error capture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CHAFSR_M_SYNDROME	(0xfUL << 16UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CHAFSR_M_SYNDROME_SHIFT	16UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Agenid Id of the foreign device causing the UE/CE errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define JPAFSR_AID		(0x1fUL << 9UL) /* jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define JPAFSR_AID_SHIFT	9UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* System bus or E-cache data ECC syndrome.  This field captures the status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * of the first occurrence of the highest-priority error according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  * E_SYND overwrite policy.  After the AFSR sticky bit, corresponding to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  * error for which the E_SYND is reported, is cleare, the contents of the E_SYND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  * field will be unchanged but will be unfrozen for further error capture.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CHAFSR_E_SYNDROME	(0x1ffUL << 0UL) /* ch,ch+,jp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CHAFSR_E_SYNDROME_SHIFT	0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* The AFSR must be explicitly cleared by software, it is not cleared automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  * by a read.  Writes to bits <51:33> with bits set will clear the corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  * bits in the AFSR.  Bits associated with disrupting traps must be cleared before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  * interrupts are re-enabled to prevent multiple traps for the same error.  I.e.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  * PSTATE.IE and AFSR bits control delivery of disrupting traps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  * Since there is only one AFAR, when multiple events have been logged by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  * bits in the AFSR, at most one of these events will have its status captured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  * in the AFAR.  The highest priority of those event bits will get AFAR logging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * The AFAR will be unlocked and available to capture the address of another event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  * as soon as the one bit in AFSR that corresponds to the event logged in AFAR is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * cleared.  For example, if AFSR.CE is detected, then AFSR.UE (which overwrites
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  * the AFAR), and AFSR.UE is cleared by not AFSR.CE, then the AFAR will be unlocked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * and ready for another event, even though AFSR.CE is still set.  The same rules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * also apply to the M_SYNDROME and E_SYNDROME fields of the AFSR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #endif /* _SPARC64_CHAFSR_H */