^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _SPARC64_BACKOFF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _SPARC64_BACKOFF_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* The macros in this file implement an exponential backoff facility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * for atomic operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * When multiple threads compete on an atomic operation, it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * possible for one thread to be continually denied a successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * completion of the compare-and-swap instruction. Heavily
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * threaded cpu implementations like Niagara can compound this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * problem even further.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * When an atomic operation fails and needs to be retried, we spin a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * certain number of times. At each subsequent failure of the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * operation we double the spin count, realizing an exponential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * backoff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * When we spin, we try to use an operation that will cause the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * current cpu strand to block, and therefore make the core fully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * available to any other other runnable strands. There are two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * options, based upon cpu capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * On all cpus prior to SPARC-T4 we do three dummy reads of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * condition code register. Each read blocks the strand for something
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * between 40 and 50 cpu cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * For SPARC-T4 and later we have a special "pause" instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * available. This is implemented using writes to register %asr27.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * The cpu will block the number of cycles written into the register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * unless a disrupting trap happens first. SPARC-T4 specifically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * implements pause with a granularity of 8 cycles. Each strand has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * an internal pause counter which decrements every 8 cycles. So the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * chip shifts the %asr27 value down by 3 bits, and writes the result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * into the pause counter. If a value smaller than 8 is written, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * chip blocks for 1 cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * To achieve the same amount of backoff as the three %ccr reads give
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * on earlier chips, we shift the backoff value up by 7 bits. (Three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * %ccr reads block for about 128 cycles, 1 << 7 == 128) We write the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * whole amount we want to block into the pause register, rather than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * loop writing 128 each time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BACKOFF_LIMIT (4 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BACKOFF_SETUP(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mov 1, reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BACKOFF_LABEL(spin_label, continue_label) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) spin_label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BACKOFF_SPIN(reg, tmp, label) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mov reg, tmp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 88: rd %ccr, %g0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) rd %ccr, %g0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) rd %ccr, %g0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .section .pause_3insn_patch,"ax";\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .word 88b; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) sllx tmp, 7, tmp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) wr tmp, 0, %asr27; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) clr tmp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .previous; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) brnz,pt tmp, 88b; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) sub tmp, 1, tmp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) set BACKOFF_LIMIT, tmp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) cmp reg, tmp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bg,pn %xcc, label; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) nop; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ba,pt %xcc, label; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) sllx reg, 1, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BACKOFF_SETUP(reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BACKOFF_LABEL(spin_label, continue_label) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) continue_label
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BACKOFF_SPIN(reg, tmp, label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif /* _SPARC64_BACKOFF_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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