Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * apb.h: Advanced PCI Bridge Configuration Registers and Bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _SPARC64_APB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _SPARC64_APB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define APB_TICK_REGISTER			0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define APB_INT_ACK				0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define APB_PRIMARY_MASTER_RETRY_LIMIT		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define APB_DMA_ASFR				0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define APB_DMA_AFAR				0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define APB_PIO_TARGET_RETRY_LIMIT		0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define APB_PIO_TARGET_LATENCY_TIMER		0xd9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define APB_DMA_TARGET_RETRY_LIMIT		0xda
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define APB_DMA_TARGET_LATENCY_TIMER		0xdb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define APB_SECONDARY_MASTER_RETRY_LIMIT	0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define APB_SECONDARY_CONTROL			0xdd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define APB_IO_ADDRESS_MAP			0xde
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define APB_MEM_ADDRESS_MAP			0xdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define APB_PCI_CONTROL_LOW			0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #  define APB_PCI_CTL_LOW_ARB_PARK			(1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #  define APB_PCI_CTL_LOW_ERRINT_EN			(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define APB_PCI_CONTROL_HIGH			0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #  define APB_PCI_CTL_HIGH_SERR				(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #  define APB_PCI_CTL_HIGH_ARBITER_EN			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define APB_PIO_ASFR				0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define APB_PIO_AFAR				0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define APB_DIAG_REGISTER			0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif /* !(_SPARC64_APB_H) */