^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/sh/mm/tlb-sh4.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * SH-4 specific TLB operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1999 Niibe Yutaka
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2002 - 2007 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) unsigned long flags, pteval, vpn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Handle debugger faulting in for debugee.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) if (vma && current->active_mm != vma->vm_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Set PTEH register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) vpn = (address & MMU_VPN_MASK) | get_asid();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) __raw_writel(vpn, MMU_PTEH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) pteval = pte.pte_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Set PTEA register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifdef CONFIG_X2TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * For the extended mode TLB this is trivial, only the ESZ and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * EPR bits need to be written out to PTEA, with the remainder of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * the protection bits (with the exception of the compat-mode SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * and PR bits, which are cleared) being written out in PTEL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) __raw_writel(pte.pte_high, MMU_PTEA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (cpu_data->flags & CPU_HAS_PTEA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* The last 3 bits and the first one of pteval contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * the PTEA timing control and space attribute bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Set PTEL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #ifdef CONFIG_CACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) pteval |= _PAGE_WT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* conveniently, we want all the software flags to be 0 anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __raw_writel(pteval, MMU_PTEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Load the TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) void local_flush_tlb_one(unsigned long asid, unsigned long page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long addr, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * NOTE: PTEH.ASID should be set to this MM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * _AND_ we need to write ASID to the array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * It would be simple if we didn't need to set PTEH.ASID...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) data = page | asid; /* VALID bit is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) jump_to_uncached();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __raw_writel(data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) back_to_cached();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void local_flush_tlb_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long flags, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Flush all the TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) jump_to_uncached();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) status = __raw_readl(MMUCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) status = ((status & MMUCR_URB) >> MMUCR_URB_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (status == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) status = MMUCR_URB_NENTRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) for (i = 0; i < status; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) back_to_cached();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ctrl_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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