^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/sh/mm/tlb-sh3.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * SH-3 specific TLB operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1999 Niibe Yutaka
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2002 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mman.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long flags, pteval, vpn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Handle debugger faulting in for debugee.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (vma && current->active_mm != vma->vm_mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Set PTEH register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) vpn = (address & MMU_VPN_MASK) | get_asid();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) __raw_writel(vpn, MMU_PTEH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) pteval = pte_val(pte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Set PTEL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* conveniently, we want all the software flags to be 0 anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __raw_writel(pteval, MMU_PTEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Load the TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) void local_flush_tlb_one(unsigned long asid, unsigned long page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long addr, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int i, ways = MMU_NTLB_WAYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * NOTE: PTEH.ASID should be set to this MM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * _AND_ we need to write ASID to the array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * It would be simple if we didn't need to set PTEH.ASID...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) addr = MMU_TLB_ADDRESS_ARRAY | (page & 0x1F000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) data = (page & 0xfffe0000) | asid; /* VALID bit is off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if ((current_cpu_data.flags & CPU_HAS_MMU_PAGE_ASSOC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) addr |= MMU_PAGE_ASSOC_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ways = 1; /* we already know the way .. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) for (i = 0; i < ways; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __raw_writel(data, addr + (i << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void local_flush_tlb_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned long flags, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Flush all the TLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Write to the MMU control register's bit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * TF-bit for SH-3, TI-bit for SH-4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * It's same position, bit #2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) status = __raw_readl(MMUCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) status |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __raw_writel(status, MMUCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ctrl_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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