Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

3 Commits   0 Branches   0 Tags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * arch/sh/mm/cache-sh3.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 1999, 2000  Niibe Yutaka
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2002 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mman.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * Write back the dirty D-caches, but not invalidate them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * Is this really worth it, or should we just alias this routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * to __flush_purge_region too?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * START: Virtual Address (U0, P1, or P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * SIZE: Size of the region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static void sh3__flush_wback_region(void *start, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	unsigned long v, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	unsigned long begin, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		& ~(L1_CACHE_BYTES-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	for (v = begin; v < end; v+=L1_CACHE_BYTES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		unsigned long addrstart = CACHE_OC_ADDRESS_ARRAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		for (j = 0; j < current_cpu_data.dcache.ways; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			unsigned long data, addr, p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			p = __pa(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 			addr = addrstart | (v & current_cpu_data.dcache.entry_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			data = __raw_readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 			if ((data & CACHE_PHYSADDR_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			    (p & CACHE_PHYSADDR_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 				data &= ~SH_CACHE_UPDATED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 				__raw_writel(data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 				local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 			addrstart += current_cpu_data.dcache.way_incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * Write back the dirty D-caches and invalidate them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * START: Virtual Address (U0, P1, or P3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * SIZE: Size of the region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static void sh3__flush_purge_region(void *start, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	unsigned long v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	unsigned long begin, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		& ~(L1_CACHE_BYTES-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	for (v = begin; v < end; v+=L1_CACHE_BYTES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		unsigned long data, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		data = (v & 0xfffffc00); /* _Virtual_ address, ~U, ~V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		addr = CACHE_OC_ADDRESS_ARRAY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			(v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		__raw_writel(data, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) void __init sh3_cache_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	__flush_wback_region = sh3__flush_wback_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	__flush_purge_region = sh3__flush_purge_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 * No write back please
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 * Except I don't think there's any way to avoid the writeback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 * So we just alias it to sh3__flush_purge_region(). dwmw2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	__flush_invalidate_region = sh3__flush_purge_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }