Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/sh/mm/cache-j2.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2015-2016 Smart Energy Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ICACHE_ENABLE	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DCACHE_ENABLE	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CACHE_ENABLE	(ICACHE_ENABLE | DCACHE_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ICACHE_FLUSH	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DCACHE_FLUSH	0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CACHE_FLUSH	(ICACHE_FLUSH | DCACHE_FLUSH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 __iomem *j2_ccr_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static void j2_flush_icache(void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	unsigned cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	for_each_possible_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		__raw_writel(CACHE_ENABLE | ICACHE_FLUSH, j2_ccr_base + cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void j2_flush_dcache(void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	unsigned cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	for_each_possible_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		__raw_writel(CACHE_ENABLE | DCACHE_FLUSH, j2_ccr_base + cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void j2_flush_both(void *args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	unsigned cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	for_each_possible_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		__raw_writel(CACHE_ENABLE | CACHE_FLUSH, j2_ccr_base + cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __init j2_cache_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	if (!j2_ccr_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	local_flush_cache_all = j2_flush_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	local_flush_cache_mm = j2_flush_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	local_flush_cache_dup_mm = j2_flush_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	local_flush_cache_page = j2_flush_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	local_flush_cache_range = j2_flush_both;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	local_flush_dcache_page = j2_flush_dcache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	local_flush_icache_range = j2_flush_icache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	local_flush_icache_page = j2_flush_icache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	local_flush_cache_sigtramp = j2_flush_icache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	pr_info("Initial J2 CCR is %.8x\n", __raw_readl(j2_ccr_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }