^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * debugfs ops for the L1 cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2006 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file "COPYING" in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) enum cache_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) CACHE_TYPE_ICACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) CACHE_TYPE_DCACHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) CACHE_TYPE_UNIFIED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int cache_seq_show(struct seq_file *file, void *iter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned int cache_type = (unsigned int)file->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct cache_info *cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int waysize, way;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned long addrstart = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Go uncached immediately so we don't skew the results any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * more than we already are..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) jump_to_uncached();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ccr = __raw_readl(SH_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if ((ccr & CCR_CACHE_ENABLE) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) back_to_cached();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) seq_printf(file, "disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (cache_type == CACHE_TYPE_DCACHE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) addrstart = CACHE_OC_ADDRESS_ARRAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) cache = ¤t_cpu_data.dcache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) addrstart = CACHE_IC_ADDRESS_ARRAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) cache = ¤t_cpu_data.icache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) waysize = cache->sets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * If the OC is already in RAM mode, we only have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * half of the entries to consider..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if ((ccr & CCR_CACHE_ORA) && cache_type == CACHE_TYPE_DCACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) waysize >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) waysize <<= cache->entry_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) for (way = 0; way < cache->ways; way++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) seq_printf(file, "-----------------------------------------\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) seq_printf(file, "Way %d\n", way);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) seq_printf(file, "-----------------------------------------\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) for (addr = addrstart, line = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) addr < addrstart + waysize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) addr += cache->linesz, line++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long data = __raw_readl(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Check the V bit, ignore invalid cachelines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if ((data & 1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* U: Dirty, cache tag is 10 bits up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) seq_printf(file, "%3d: %c 0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) line, data & 2 ? 'U' : ' ',
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) data & 0x1ffffc00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) addrstart += cache->way_incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) back_to_cached();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int cache_debugfs_open(struct inode *inode, struct file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return single_open(file, cache_seq_show, inode->i_private);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct file_operations cache_debugfs_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .open = cache_debugfs_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .read = seq_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .llseek = seq_lseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .release = single_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int __init cache_debugfs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) debugfs_create_file("dcache", S_IRUSR, arch_debugfs_dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) (void *)CACHE_TYPE_DCACHE, &cache_debugfs_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) debugfs_create_file("icache", S_IRUSR, arch_debugfs_dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) (void *)CACHE_TYPE_ICACHE, &cache_debugfs_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) module_init(cache_debugfs_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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