Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) menu "Memory management options"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) config MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)         bool "Support for memory management hardware"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 	depends on !CPU_SH2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 	  Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 	  boot on these systems, this option must not be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	  On other systems (such as the SH-3 and 4) where an MMU exists,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	  turning this off will boot the kernel on these machines with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	  MMU implicitly switched off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) config PAGE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	hex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	default "0x80000000" if MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	default "0x00000000"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) config FORCE_MAX_ZONEORDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	int "Maximum zone order"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	range 9 64 if PAGE_SIZE_16KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	default "9" if PAGE_SIZE_16KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	range 7 64 if PAGE_SIZE_64KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	default "7" if PAGE_SIZE_64KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	range 11 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	default "14" if !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	default "11"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	  The kernel memory allocator divides physically contiguous memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	  blocks into "zones", where each zone is a power of two number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	  pages.  This option selects the largest power of two that the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	  keeps in the memory allocator.  If you need to allocate very large
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	  blocks of physically contiguous memory, then you may need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	  increase this value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	  This config option is actually maximum order plus one. For example,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	  a value of 11 means that the largest free memory block is 2^10 pages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	  The page size is not necessarily 4KB. Keep this in mind when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	  choosing a value for this option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) config MEMORY_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	hex "Physical memory start address"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	default "0x08000000"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	  Computers built with Hitachi SuperH processors always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	  map the ROM starting at address zero.  But the processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	  does not specify the range that RAM takes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	  The physical memory (RAM) start address will be automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	  set to 08000000. Other platforms, such as the Solution Engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	  boards typically map RAM at 0C000000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	  Tweak this only when porting to a new machine which does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	  already have a defconfig. Changing it from the known correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	  value on any of the known systems will only lead to disaster.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) config MEMORY_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	hex "Physical memory size"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	default "0x04000000"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	  This sets the default memory size assumed by your SH kernel. It can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	  be overridden as normal by the 'mem=' argument on the kernel command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	  line. If unsure, consult your board specifications or just leave it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	  as 0x04000000 which was the default value before this became
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	  configurable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) # Physical addressing modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) config 29BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	def_bool !32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	select UNCACHED_MAPPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) config 32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	default !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) config PMB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	bool "Support 32-bit physical addressing through PMB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	select 32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	select UNCACHED_MAPPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	  If you say Y here, physical addressing will be extended to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	  32-bits through the SH-4A PMB. If this is not set, legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	  29-bit physical addressing will be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) config X2TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	depends on (CPU_SHX2 || CPU_SHX3) && MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) config VSYSCALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	bool "Support vsyscall page"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	depends on MMU && (CPU_SH3 || CPU_SH4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	  This will enable support for the kernel mapping a vDSO page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	  in process space, and subsequently handing down the entry point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	  to the libc through the ELF auxiliary vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	  From the kernel side this is used for the signal trampoline.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	  For systems with an MMU that can afford to give up a page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	  (the default value) say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) config NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	bool "Non Uniform Memory Access (NUMA) Support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	depends on MMU && SYS_SUPPORTS_NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	select ARCH_WANT_NUMA_VARIABLE_LOCALITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	default n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	  Some SH systems have many various memories scattered around
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	  the address space, each with varying latencies. This enables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	  support for these blocks by binding them to nodes and allowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	  memory policies to be used for prioritizing and controlling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	  allocation behaviour.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) config NODES_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	default "3" if CPU_SUBTYPE_SHX3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	default "1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	depends on NEED_MULTIPLE_NODES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) config ARCH_FLATMEM_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	depends on !NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) config ARCH_SPARSEMEM_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	select SPARSEMEM_STATIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) config ARCH_SPARSEMEM_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) config ARCH_SELECT_MEMORY_MODEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) config ARCH_ENABLE_MEMORY_HOTPLUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	depends on SPARSEMEM && MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) config ARCH_ENABLE_MEMORY_HOTREMOVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	depends on SPARSEMEM && MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) config ARCH_MEMORY_PROBE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	depends on MEMORY_HOTPLUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) config IOREMAP_FIXED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)        def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)        depends on X2TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) config UNCACHED_MAPPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) config HAVE_SRAM_POOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	select GENERIC_ALLOCATOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	prompt "Kernel page size"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	default PAGE_SIZE_4KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) config PAGE_SIZE_4KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	bool "4kB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	  This is the default page size used by all SuperH CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) config PAGE_SIZE_8KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	bool "8kB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	depends on !MMU || X2TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	  This enables 8kB pages as supported by SH-X2 and later MMUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) config PAGE_SIZE_16KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	bool "16kB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	depends on !MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	  This enables 16kB pages on MMU-less SH systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) config PAGE_SIZE_64KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	bool "64kB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	depends on !MMU || CPU_SH4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	  This enables support for 64kB pages, possible on all SH-4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	  CPUs and later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	prompt "HugeTLB page size"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	depends on HUGETLB_PAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	default HUGETLB_PAGE_SIZE_1MB if PAGE_SIZE_64KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	default HUGETLB_PAGE_SIZE_64K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) config HUGETLB_PAGE_SIZE_64K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	bool "64kB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	depends on !PAGE_SIZE_64KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) config HUGETLB_PAGE_SIZE_256K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	bool "256kB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	depends on X2TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) config HUGETLB_PAGE_SIZE_1MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	bool "1MB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) config HUGETLB_PAGE_SIZE_4MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	bool "4MB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	depends on X2TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) config HUGETLB_PAGE_SIZE_64MB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	bool "64MB"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	depends on X2TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) config SCHED_MC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	bool "Multi-core scheduler support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	depends on SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	  Multi-core scheduler support improves the CPU scheduler's decision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	  making when dealing with multi-core CPU chips at a cost of slightly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	  increased overhead in some places. If unsure say N here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) endmenu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) menu "Cache configuration"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) config SH7705_CACHE_32KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	bool "Enable 32KB cache size for SH7705"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	depends on CPU_SUBTYPE_SH7705
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) choice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	prompt "Cache mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	default CACHE_WRITEBACK if CPU_SH2A || CPU_SH3 || CPU_SH4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	default CACHE_WRITETHROUGH if (CPU_SH2 && !CPU_SH2A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) config CACHE_WRITEBACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	bool "Write-back"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) config CACHE_WRITETHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	bool "Write-through"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	  Selecting this option will configure the caches in write-through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	  mode, as opposed to the default write-back configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	  Since there's sill some aliasing issues on SH-4, this option will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	  unfortunately still require the majority of flushing functions to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	  be implemented to deal with aliasing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	  If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) config CACHE_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	bool "Off"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) endchoice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) endmenu