Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *	Precise Delay Loops for SuperH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	Copyright (C) 1999 Niibe Yutaka & Kaz Kojima
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) void __delay(unsigned long loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	__asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 		 * ST40-300 appears to have an issue with this code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		 * normally taking two cycles each loop, as with all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		 * other SH variants. If however the branch and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		 * delay slot straddle an 8 byte boundary, this increases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		 * to 3 cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		 * This align directive ensures this doesn't occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		".balign 8\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		"tst	%0, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		"1:\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		"bf/s	1b\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		" dt	%0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		: "=r" (loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		: "0" (loops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		: "t");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) inline void __const_udelay(unsigned long xloops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	xloops *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	__asm__("dmulu.l	%0, %2\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		"sts	mach, %0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		: "=r" (xloops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		: "0" (xloops),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		  "r" (cpu_data[raw_smp_processor_id()].loops_per_jiffy * (HZ/4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		: "macl", "mach");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	__delay(++xloops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void __udelay(unsigned long usecs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	__const_udelay(usecs * 0x000010c6);  /* 2**32 / 1000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void __ndelay(unsigned long nsecs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	__const_udelay(nsecs * 0x00000005);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)