Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Performance event support framework for SuperH hardware counters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2009  Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Heavily based on the x86 and PowerPC implementations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * x86:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  Copyright (C) 2009 Jaswinder Singh Rajput
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * ppc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *  Copyright 2008-2009 Paul Mackerras, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) struct cpu_hw_events {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	struct perf_event	*events[MAX_HWEVENTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	unsigned long		used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	unsigned long		active_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static struct sh_pmu *sh_pmu __read_mostly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* Number of perf_events counting hardware events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static atomic_t num_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* Used to avoid races in calling reserve/release_pmc_hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static DEFINE_MUTEX(pmc_reserve_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * Stub these out for now, do something more profound later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) int reserve_pmc_hardware(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) void release_pmc_hardware(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static inline int sh_pmu_initialized(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return !!sh_pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) const char *perf_pmu_name(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (!sh_pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return sh_pmu->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) EXPORT_SYMBOL_GPL(perf_pmu_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) int perf_num_counters(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (!sh_pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return sh_pmu->num_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) EXPORT_SYMBOL_GPL(perf_num_counters);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * Release the PMU if this is the last perf_event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static void hw_perf_event_destroy(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (!atomic_add_unless(&num_events, -1, 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		mutex_lock(&pmc_reserve_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		if (atomic_dec_return(&num_events) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			release_pmc_hardware();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		mutex_unlock(&pmc_reserve_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static int hw_perf_cache_event(int config, int *evp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	unsigned long type, op, result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	int ev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (!sh_pmu->cache_events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* unpack config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	type = config & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	op = (config >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	result = (config >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (type >= PERF_COUNT_HW_CACHE_MAX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	    op >= PERF_COUNT_HW_CACHE_OP_MAX ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	    result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ev = (*sh_pmu->cache_events)[type][op][result];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	if (ev == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	if (ev == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	*evp = ev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int __hw_perf_event_init(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct perf_event_attr *attr = &event->attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	int config = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (!sh_pmu_initialized())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	 * See if we need to reserve the counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	 * If no events are currently in use, then we have to take a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	 * mutex to ensure that we don't race with another task doing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	 * reserve_pmc_hardware or release_pmc_hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (!atomic_inc_not_zero(&num_events)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		mutex_lock(&pmc_reserve_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		if (atomic_read(&num_events) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		    reserve_pmc_hardware())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			atomic_inc(&num_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		mutex_unlock(&pmc_reserve_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	event->destroy = hw_perf_event_destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	switch (attr->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	case PERF_TYPE_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		config = attr->config & sh_pmu->raw_event_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	case PERF_TYPE_HW_CACHE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		err = hw_perf_cache_event(attr->config, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	case PERF_TYPE_HARDWARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		if (attr->config >= sh_pmu->max_events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		config = sh_pmu->event_map(attr->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (config == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	hwc->config |= config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void sh_perf_event_update(struct perf_event *event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				   struct hw_perf_event *hwc, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u64 prev_raw_count, new_raw_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	s64 delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	int shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	 * Depending on the counter configuration, they may or may not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 * be chained, in which case the previous counter value can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	 * updated underneath us if the lower-half overflows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	 * Our tactic to handle this is to first atomically read and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	 * exchange a new raw count - then add that new-prev delta
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	 * count to the generic counter atomically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * As there is no interrupt associated with the overflow events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * this is the simplest approach for maintaining consistency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	prev_raw_count = local64_read(&hwc->prev_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	new_raw_count = sh_pmu->read(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			     new_raw_count) != prev_raw_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	 * Now we have the new raw value and have updated the prev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 * timestamp already. We can now calculate the elapsed delta
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	 * (counter-)time and add that to the generic counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	 * Careful, not all hw sign-extends above the physical width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 * of the count.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	delta = (new_raw_count << shift) - (prev_raw_count << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	delta >>= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	local64_add(delta, &event->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void sh_pmu_stop(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	int idx = hwc->idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (!(event->hw.state & PERF_HES_STOPPED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		sh_pmu->disable(hwc, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		cpuc->events[idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		event->hw.state |= PERF_HES_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		sh_perf_event_update(event, &event->hw, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		event->hw.state |= PERF_HES_UPTODATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void sh_pmu_start(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	int idx = hwc->idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (WARN_ON_ONCE(idx == -1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (flags & PERF_EF_RELOAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	cpuc->events[idx] = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	event->hw.state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	sh_pmu->enable(hwc, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void sh_pmu_del(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	sh_pmu_stop(event, PERF_EF_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	__clear_bit(event->hw.idx, cpuc->used_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	perf_event_update_userpage(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int sh_pmu_add(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	struct hw_perf_event *hwc = &event->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	int idx = hwc->idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	int ret = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	perf_pmu_disable(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (__test_and_set_bit(idx, cpuc->used_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		idx = find_first_zero_bit(cpuc->used_mask, sh_pmu->num_events);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		if (idx == sh_pmu->num_events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		__set_bit(idx, cpuc->used_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		hwc->idx = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	sh_pmu->disable(hwc, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (flags & PERF_EF_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		sh_pmu_start(event, PERF_EF_RELOAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	perf_event_update_userpage(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	perf_pmu_enable(event->pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void sh_pmu_read(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	sh_perf_event_update(event, &event->hw, event->hw.idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int sh_pmu_event_init(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	/* does not support taken branch sampling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	if (has_branch_stack(event))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	switch (event->attr.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	case PERF_TYPE_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	case PERF_TYPE_HW_CACHE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	case PERF_TYPE_HARDWARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		err = __hw_perf_event_init(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (unlikely(err)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		if (event->destroy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			event->destroy(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void sh_pmu_enable(struct pmu *pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (!sh_pmu_initialized())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	sh_pmu->enable_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static void sh_pmu_disable(struct pmu *pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	if (!sh_pmu_initialized())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	sh_pmu->disable_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static struct pmu pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.pmu_enable	= sh_pmu_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.pmu_disable	= sh_pmu_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.event_init	= sh_pmu_event_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.add		= sh_pmu_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.del		= sh_pmu_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.start		= sh_pmu_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.stop		= sh_pmu_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	.read		= sh_pmu_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int sh_pmu_prepare_cpu(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	memset(cpuhw, 0, sizeof(struct cpu_hw_events));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int register_sh_pmu(struct sh_pmu *_pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (sh_pmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	sh_pmu = _pmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	pr_info("Performance Events: %s support registered\n", _pmu->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	 * All of the on-chip counters are "limited", in that they have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	 * no interrupts, and are therefore unable to do sampling without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	 * further work and timer assistance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	WARN_ON(_pmu->num_events > MAX_HWEVENTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	cpuhp_setup_state(CPUHP_PERF_SUPERH, "PERF_SUPERH", sh_pmu_prepare_cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			  NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }