^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * $Id: head.S,v 1.7 2003/09/01 17:58:19 lethal Exp $
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * arch/sh/kernel/head.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2010 Matt Fleming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Head.S contains the SH exception handlers and startup code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <cpu/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifdef CONFIG_CPU_SH4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SYNCO() synco
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PREFI(label, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) mov.l label, reg; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) prefi @reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SYNCO()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PREFI(label, reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .section .empty_zero_page, "aw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) ENTRY(empty_zero_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .long 1 /* MOUNT_ROOT_RDONLY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .long 0 /* RAMDISK_FLAGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .long 0x0200 /* ORIG_ROOT_DEV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .long 1 /* LOADER_TYPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .long 0x00000000 /* INITRD_START */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .long 0x00000000 /* INITRD_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #ifdef CONFIG_32BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .long 0x53453f00 + 32 /* "SE?" = 32 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .long 0x53453f00 + 29 /* "SE?" = 29 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .skip PAGE_SIZE - empty_zero_page - 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) __HEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Condition at the entry of _stext:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * BSC has already been initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * INTC may or may not be initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * VBR may or may not be initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * MMU may or may not be initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Cache may or may not be initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Hardware (including on-chip modules) may or may not be initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ENTRY(_stext)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ! Initialize Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mov.l 1f, r0 ! MD=1, RB=0, BL=0, IMASK=0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ldc r0, sr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ! Initialize global interrupt mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #ifdef CONFIG_CPU_HAS_SR_RB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) mov #0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ldc r0, r6_bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #ifdef CONFIG_OF_FLATTREE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mov r4, r12 ! Store device tree blob pointer in r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * Prefetch if possible to reduce cache miss penalty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * We do this early on for SH-4A as a micro-optimization,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * as later on we will have speculative execution enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * and this will become less of an issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PREFI(5f, r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PREFI(6f, r0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) !
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mov.l 2f, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mov r0, r15 ! Set initial r15 (stack pointer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #ifdef CONFIG_CPU_HAS_SR_RB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mov.l 7f, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ldc r0, r7_bank ! ... and initial thread_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #ifdef CONFIG_PMB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Reconfigure the initial PMB mappings setup by the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * When we boot in 32-bit MMU mode there are 2 PMB entries already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * setup for us.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * Entry VPN PPN V SZ C UB WT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * ---------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * 0 0x80000000 0x00000000 1 512MB 1 0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * 1 0xA0000000 0x00000000 1 512MB 0 0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * But we reprogram them here because we want complete control over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * our address space and the initial mappings may not map PAGE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * to __MEMORY_START (or even map all of our RAM).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Once we've setup cached and uncached mappings we clear the rest of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * PMB entries. This clearing also deals with the fact that PMB entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * can persist across reboots. The PMB could have been left in any state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * when the reboot occurred, so to be safe we clear all entries and start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * with with a clean slate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * The uncached mapping is constructed using the smallest possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * mapping with a single unbufferable page. Only the kernel text needs to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * be covered via the uncached mapping so that certain functions can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * run uncached.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Drivers and the like that have previously abused the 1:1 identity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * mapping are unsupported in 32-bit mode and must specify their caching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * preference when page tables are constructed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * This frees up the P2 space for more nefarious purposes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Register utilization is as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * r0 = PMB_DATA data field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * r1 = PMB_DATA address field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * r2 = PMB_ADDR data field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * r3 = PMB_ADDR address field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * r4 = PMB_E_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * r5 = remaining amount of RAM to map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * r6 = PMB mapping size we're trying to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * r7 = cached_to_uncached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * r8 = scratch register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * r9 = scratch register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * r10 = number of PMB entries we've setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * r11 = scratch register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mov.l .LMMUCR, r1 /* Flush the TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mov.l @r1, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) or #MMUCR_TI, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mov.l r0, @r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mov.l .LMEMORY_SIZE, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mov #PMB_E_SHIFT, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mov #0x1, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) shld r0, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mov.l .LFIRST_DATA_ENTRY, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mov.l .LPMB_DATA, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mov.l .LFIRST_ADDR_ENTRY, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mov.l .LPMB_ADDR, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * First we need to walk the PMB and figure out if there are any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * existing mappings that match the initial mappings VPN/PPN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * If these have already been established by the bootloader, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * don't bother setting up new entries here, and let the late PMB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * initialization take care of things instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Note that we may need to coalesce and merge entries in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * to reclaim more available PMB slots, which is much more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * we want to do at this early stage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) mov #0, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) mov #NR_PMB_ENTRIES, r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mov r1, r7 /* temporary PMB_DATA iter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .Lvalidate_existing_mappings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) mov.l .LPMB_DATA_MASK, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mov.l @r7, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) and r11, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) cmp/eq r0, r8 /* Check for valid __MEMORY_START mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) bt .Lpmb_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) add #1, r10 /* Increment the loop counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cmp/eq r9, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) bf/s .Lvalidate_existing_mappings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) add r4, r7 /* Increment to the next PMB_DATA entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * If we've fallen through, continue with setting up the initial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * mappings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mov r5, r7 /* cached_to_uncached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mov #0, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #ifdef CONFIG_UNCACHED_MAPPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * Uncached mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mov #(PMB_SZ_16M >> 2), r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) shll2 r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mov #(PMB_UB >> 8), r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) shll8 r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) or r0, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) or r9, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mov.l r8, @r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mov r2, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) add r7, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) mov.l r8, @r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) add r4, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) add r4, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) add #1, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Iterate over all of the available sizes from largest to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * smallest for constructing the cached mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define __PMB_ITER_BY_SIZE(size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .L##size: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mov #(size >> 4), r6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) shll16 r6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) shll8 r6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) cmp/hi r5, r6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) bt 9999f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mov #(PMB_SZ_##size##M >> 2), r9; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) shll2 r9; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Cached mapping \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mov #PMB_C, r8; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) or r0, r8; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) or r9, r8; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) mov.l r8, @r1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mov.l r2, @r3; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Increment to the next PMB_DATA entry */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) add r4, r1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Increment to the next PMB_ADDR entry */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) add r4, r3; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Increment number of PMB entries */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) add #1, r10; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) sub r6, r5; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) add r6, r0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) add r6, r2; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) bra .L##size; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 9999:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) __PMB_ITER_BY_SIZE(512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) __PMB_ITER_BY_SIZE(128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) __PMB_ITER_BY_SIZE(64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) __PMB_ITER_BY_SIZE(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #ifdef CONFIG_UNCACHED_MAPPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * Now that we can access it, update cached_to_uncached and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * uncached_size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mov.l .Lcached_to_uncached, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mov.l r7, @r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mov.l .Luncached_size, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mov #1, r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) shll16 r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) shll8 r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mov.l r7, @r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * Clear the remaining PMB entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * r3 = entry to begin clearing from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * r10 = number of entries we've setup so far
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mov #0, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mov #NR_PMB_ENTRIES, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .Lagain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mov.l r1, @r3 /* Clear PMB_ADDR entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) add #1, r10 /* Increment the loop counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) cmp/eq r0, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) bf/s .Lagain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) add r4, r3 /* Increment to the next PMB_ADDR entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mov.l 6f, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) icbi @r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .Lpmb_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #endif /* CONFIG_PMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #ifndef CONFIG_SH_NO_BSS_INIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Don't clear BSS if running on slow platforms such as an RTL simulation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * remote memory via SHdebug link, etc. For these the memory can be guaranteed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * to be all zero on boot anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ! Clear BSS area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mov.l 3f, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) cmp/eq #0, r0 ! skip clear if set to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) bt 10f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) mov.l 3f, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) add #4, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mov.l 4f, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mov #0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 9: cmp/hs r2, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) bf/s 9b ! while (r1 < r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) mov.l r0,@-r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #ifdef CONFIG_OF_FLATTREE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) mov.l 8f, r0 ! Make flat device tree available early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) jsr @r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mov r12, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ! Additional CPU initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) mov.l 6f, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) jsr @r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) SYNCO() ! Wait for pending instructions..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ! Start kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mov.l 5f, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) jmp @r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .balign 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #if defined(CONFIG_CPU_SH2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 1: .long 0x000000F0 ! IMASK=0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 1: .long 0x500080F0 ! MD=1, RB=0, BL=1, FD=1, IMASK=0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ENTRY(stack_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 2: .long init_thread_union+THREAD_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 3: .long __bss_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 4: .long _end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 5: .long start_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 6: .long cpu_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 7: .long init_thread_union
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #if defined(CONFIG_OF_FLATTREE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 8: .long sh_fdt_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #ifdef CONFIG_PMB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .LPMB_ADDR: .long PMB_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .LPMB_DATA: .long PMB_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .LPMB_DATA_MASK: .long PMB_PFN_MASK | PMB_V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .LFIRST_ADDR_ENTRY: .long PAGE_OFFSET | PMB_V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .LFIRST_DATA_ENTRY: .long __MEMORY_START | PMB_V
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .LMMUCR: .long MMUCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .LMEMORY_SIZE: .long __MEMORY_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #ifdef CONFIG_UNCACHED_MAPPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .Lcached_to_uncached: .long cached_to_uncached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .Luncached_size: .long uncached_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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