Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * arch/sh/kernel/cpu/init.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * CPU init code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2002 - 2009  Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2003  Richard Curnow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/elf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/sh_bios.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #ifdef CONFIG_SH_FPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define cpu_has_fpu	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define cpu_has_fpu	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #ifdef CONFIG_SH_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define cpu_has_dsp	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define cpu_has_dsp	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * Generic wrapper for command line arguments to disable on-chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * peripherals (nofpu, nodsp, and so forth).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define onchip_setup(x)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static int x##_disabled = !cpu_has_##x;			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static int x##_setup(char *opts)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	x##_disabled = 1;				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	return 1;					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) }							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) __setup("no" __stringify(x), x##_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) onchip_setup(fpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) onchip_setup(dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #ifdef CONFIG_SPECULATIVE_EXECUTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CPUOPM		0xff2f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CPUOPM_RABD	(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static void speculative_execution_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	/* Clear RABD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	__raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	/* Flush the update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	(void)__raw_readl(CPUOPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ctrl_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define speculative_execution_init()	do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #ifdef CONFIG_CPU_SH4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define EXPMASK			0xff2f0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define EXPMASK_RTEDS		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define EXPMASK_BRDSSLP		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define EXPMASK_MMCAW		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) static void expmask_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	unsigned long expmask = __raw_readl(EXPMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	 * Future proofing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * Disable support for slottable sleep instruction, non-nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 * instructions in the rte delay slot, and associative writes to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 * the memory-mapped cache array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	expmask &= ~(EXPMASK_RTEDS | EXPMASK_BRDSSLP | EXPMASK_MMCAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	__raw_writel(expmask, EXPMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	ctrl_barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define expmask_init()	do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) /* 2nd-level cache init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) void __attribute__ ((weak)) l2_cache_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * Generic first-level cache init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #if !defined(CONFIG_CPU_J2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void cache_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	unsigned long ccr, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	jump_to_uncached();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	ccr = __raw_readl(SH_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	 * At this point we don't know whether the cache is enabled or not - a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	 * bootloader may have enabled it.  There are at least 2 things that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 * could be dirty in the cache at this point:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 * 1. kernel command line set up by boot loader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 * 2. spilled registers from the prolog of this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 * => before re-initialising the cache, we must do a purge of the whole
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 * cache out to memory for safety.  As long as nothing is spilled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 * during the loop to lines that have already been done, this is safe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	 * - RPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (ccr & CCR_CACHE_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		unsigned long ways, waysize, addrstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		waysize = current_cpu_data.dcache.sets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #ifdef CCR_CACHE_ORA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		 * If the OC is already in RAM mode, we only have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		 * half of the entries to flush..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		if (ccr & CCR_CACHE_ORA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			waysize >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		waysize <<= current_cpu_data.dcache.entry_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #ifdef CCR_CACHE_EMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		/* If EMODE is not set, we only have 1 way to flush. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		if (!(ccr & CCR_CACHE_EMODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			ways = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			ways = current_cpu_data.dcache.ways;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		addrstart = CACHE_OC_ADDRESS_ARRAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			for (addr = addrstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			     addr < addrstart + waysize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			     addr += current_cpu_data.dcache.linesz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 				__raw_writel(0, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			addrstart += current_cpu_data.dcache.way_incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		} while (--ways);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	 * Default CCR values .. enable the caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 * and invalidate them immediately..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #ifdef CCR_CACHE_EMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/* Force EMODE if possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (current_cpu_data.dcache.ways > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		flags |= CCR_CACHE_EMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		flags &= ~CCR_CACHE_EMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #if defined(CONFIG_CACHE_WRITETHROUGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	/* Write-through */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	flags |= CCR_CACHE_WT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #elif defined(CONFIG_CACHE_WRITEBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* Write-back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	flags |= CCR_CACHE_CB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	flags &= ~CCR_CACHE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	l2_cache_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	__raw_writel(flags, SH_CCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	back_to_cached();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define cache_init()	do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CSHAPE(totalsize, linesize, assoc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	((totalsize & ~0xff) | (linesize << 4) | assoc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CACHE_DESC_SHAPE(desc)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void detect_cache_shape(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		l1i_cache_shape = l1d_cache_shape;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (current_cpu_data.flags & CPU_HAS_L2_CACHE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		l2_cache_shape = -1; /* No S-cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void fpu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/* Disable the FPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (fpu_disabled && (current_cpu_data.flags & CPU_HAS_FPU)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		printk("FPU Disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		current_cpu_data.flags &= ~CPU_HAS_FPU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	disable_fpu();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	clear_used_math();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #ifdef CONFIG_SH_DSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void release_dsp(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	unsigned long sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/* Clear SR.DSP bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	__asm__ __volatile__ (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		"stc\tsr, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		"and\t%1, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		"ldc\t%0, sr\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		: "=&r" (sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		: "r" (~SR_DSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void dsp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	unsigned long sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	 * Set the SR.DSP bit, wait for one instruction, and then read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	 * back the SR value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	__asm__ __volatile__ (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		"stc\tsr, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		"or\t%1, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		"ldc\t%0, sr\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		"nop\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		"stc\tsr, %0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		: "=&r" (sr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		: "r" (SR_DSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* If the DSP bit is still set, this CPU has a DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (sr & SR_DSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		current_cpu_data.flags |= CPU_HAS_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	/* Disable the DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (dsp_disabled && (current_cpu_data.flags & CPU_HAS_DSP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		printk("DSP Disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		current_cpu_data.flags &= ~CPU_HAS_DSP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	/* Now that we've determined the DSP status, clear the DSP bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	release_dsp();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static inline void dsp_init(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #endif /* CONFIG_SH_DSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  * cpu_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  * This is our initial entry point for each CPU, and is invoked on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)  * boot CPU prior to calling start_kernel(). For SMP, a combination of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  * this and start_secondary() will bring up each processor to a ready
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  * state prior to hand forking the idle loop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  * We do all of the basic processor init here, including setting up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  * the caches, FPU, DSP, etc. By the time start_kernel() is hit (and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  * subsequently platform_setup()) things like determining the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  * subtype and initial configuration will all be done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)  * Each processor family is still responsible for doing its own probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)  * and cache configuration in cpu_probe().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) asmlinkage void cpu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	current_thread_info()->cpu = hard_smp_processor_id();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/* First, probe the CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	cpu_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (current_cpu_data.type == CPU_SH_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		panic("Unknown CPU");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	/* First setup the rest of the I-cache info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 				      current_cpu_data.icache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 				    current_cpu_data.icache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	/* And the D-cache too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 				      current_cpu_data.dcache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 				    current_cpu_data.dcache.linesz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	/* Init the cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	cache_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (raw_smp_processor_id() == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		shm_align_mask = max_t(unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 				       current_cpu_data.dcache.way_size - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 				       PAGE_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		shm_align_mask = PAGE_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		/* Boot CPU sets the cache shape */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		detect_cache_shape();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	fpu_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	dsp_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	 * Initialize the per-CPU ASID cache very early, since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	 * TLB flushing routines depend on this being setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	current_cpu_data.asid_cache = NO_CONTEXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	current_cpu_data.phys_bits = __in_29bit_mode() ? 29 : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	speculative_execution_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	expmask_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	/* Do the rest of the boot processor setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (raw_smp_processor_id() == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		/* Save off the BIOS VBR, if there is one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		sh_bios_vbr_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		 * Setup VBR for boot CPU. Secondary CPUs do this through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		 * start_secondary().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		per_cpu_trap_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		 * Boot processor to setup the FP and extended state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		 * context info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		init_thread_xstate();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }