Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <asm/clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) static struct clk master_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	.flags		= CLK_ENABLE_ON_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	.rate		= CONFIG_SH_PCLK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static struct clk peripheral_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	.parent		= &master_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	.flags		= CLK_ENABLE_ON_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static struct clk bus_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	.parent		= &master_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	.flags		= CLK_ENABLE_ON_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static struct clk cpu_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	.parent		= &master_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	.flags		= CLK_ENABLE_ON_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)  * The ordering of these clocks matters, do not change it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct clk *onchip_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	&master_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	&peripheral_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	&bus_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	&cpu_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct clk_lookup lookups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	/* main clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	CLKDEV_CON_ID("master_clk", &master_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	CLKDEV_CON_ID("peripheral_clk", &peripheral_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	CLKDEV_CON_ID("bus_clk", &bus_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	CLKDEV_CON_ID("cpu_clk", &cpu_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int __init __deprecated cpg_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		struct clk *clk = onchip_clocks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		arch_init_clk_ops(&clk->ops, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		if (clk->ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			ret |= clk_register(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	clk_add_alias("fck", "sh-tmu-sh3.0", "peripheral_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	clk_add_alias("fck", "sh-tmu.0", "peripheral_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	clk_add_alias("fck", "sh-tmu.1", "peripheral_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	clk_add_alias("fck", "sh-tmu.2", "peripheral_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	clk_add_alias("fck", "sh-mtu2", "peripheral_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	clk_add_alias("fck", "sh-cmt-16.0", "peripheral_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	clk_add_alias("fck", "sh-cmt-32.0", "peripheral_clk", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)  * Placeholder for compatibility, until the lazy CPUs do this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)  * on their own.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int __init __weak arch_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	return cpg_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }