^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * include/asm-sh/watchdog.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2002, 2003 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009 Siemens AG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009 Valentin Sitdikov
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __ASM_SH_WATCHDOG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ASM_SH_WATCHDOG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define WTCNT_HIGH 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define WTCSR_HIGH 0xa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define WTCSR_CKS2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define WTCSR_CKS1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define WTCSR_CKS0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <cpu/watchdog.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * See cpu-sh2/watchdog.h for explanation of this stupidity..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifndef WTCNT_R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) # define WTCNT_R WTCNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifndef WTCSR_R
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) # define WTCSR_R WTCSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * CKS0-2 supports a number of clock division ratios. At the time the watchdog
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * is enabled, it defaults to a 41 usec overflow period .. we overload this to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * something a little more reasonable, and really can't deal with anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * lower than WTCSR_CKS_1024, else we drop back into the usec range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Clock Division Ratio Overflow Period
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * --------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * 1/32 (initial value) 41 usecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * 1/64 82 usecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * 1/128 164 usecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 1/256 328 usecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * 1/512 656 usecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * 1/1024 1.31 msecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 1/2048 2.62 msecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 1/4096 5.25 msecs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define WTCSR_CKS_32 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define WTCSR_CKS_64 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define WTCSR_CKS_128 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define WTCSR_CKS_256 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define WTCSR_CKS_512 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define WTCSR_CKS_1024 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define WTCSR_CKS_2048 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define WTCSR_CKS_4096 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #if defined(CONFIG_CPU_SUBTYPE_SH7785) || defined(CONFIG_CPU_SUBTYPE_SH7780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * sh_wdt_read_cnt - Read from Counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Reads back the WTCNT value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline __u32 sh_wdt_read_cnt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return __raw_readl(WTCNT_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * sh_wdt_write_cnt - Write to Counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @val: Value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Writes the given value @val to the lower byte of the timer counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * The upper byte is set manually on each write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static inline void sh_wdt_write_cnt(__u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * sh_wdt_write_bst - Write to Counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @val: Value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Writes the given value @val to the lower byte of the timer counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * The upper byte is set manually on each write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static inline void sh_wdt_write_bst(__u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * sh_wdt_read_csr - Read from Control/Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Reads back the WTCSR value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static inline __u32 sh_wdt_read_csr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return __raw_readl(WTCSR_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * sh_wdt_write_csr - Write to Control/Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @val: Value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Writes the given value @val to the lower byte of the control/status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * register. The upper byte is set manually on each write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static inline void sh_wdt_write_csr(__u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __raw_writel((WTCSR_HIGH << 24) | (__u32)val, WTCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * sh_wdt_read_cnt - Read from Counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Reads back the WTCNT value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static inline __u8 sh_wdt_read_cnt(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return __raw_readb(WTCNT_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * sh_wdt_write_cnt - Write to Counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @val: Value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * Writes the given value @val to the lower byte of the timer counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * The upper byte is set manually on each write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static inline void sh_wdt_write_cnt(__u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __raw_writew((WTCNT_HIGH << 8) | (__u16)val, WTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * sh_wdt_read_csr - Read from Control/Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Reads back the WTCSR value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline __u8 sh_wdt_read_csr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return __raw_readb(WTCSR_R);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * sh_wdt_write_csr - Write to Control/Status Register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @val: Value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Writes the given value @val to the lower byte of the control/status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * register. The upper byte is set manually on each write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline void sh_wdt_write_csr(__u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __raw_writew((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif /* CONFIG_CPU_SUBTYPE_SH7785 || CONFIG_CPU_SUBTYPE_SH7780 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif /* __ASM_SH_WATCHDOG_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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