^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ASM_SH_SMC37C93X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ASM_SH_SMC37C93X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * linux/include/asm-sh/smc37c93x.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2000 Kazumoto Kojima
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * SMSC 37C93x Super IO Chip support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Default base I/O address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define FDC_PRIMARY_BASE 0x3f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IDE1_PRIMARY_BASE 0x1f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IDE1_SECONDARY_BASE 0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PARPORT_PRIMARY_BASE 0x378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define COM1_PRIMARY_BASE 0x2f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define COM2_PRIMARY_BASE 0x3f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RTC_PRIMARY_BASE 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define KBC_PRIMARY_BASE 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AUXIO_PRIMARY_BASE 0x000 /* XXX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Logical device number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LDN_FDC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LDN_IDE1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LDN_IDE2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LDN_PARPORT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LDN_COM1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LDN_COM2 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LDN_RTC 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LDN_KBC 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LDN_AUXIO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Configuration port and key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CONFIG_PORT 0x3f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define INDEX_PORT CONFIG_PORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DATA_PORT 0x3f1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CONFIG_ENTER 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CONFIG_EXIT 0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Configuration index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CURRENT_LDN_INDEX 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define POWER_CONTROL_INDEX 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ACTIVATE_INDEX 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IO_BASE_HI_INDEX 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IO_BASE_LO_INDEX 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IRQ_SELECT_INDEX 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DMA_SELECT_INDEX 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GPIO46_INDEX 0xc6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GPIO47_INDEX 0xc7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* UART stuff. Only for debugging. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* UART Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define UART_IER 0x2 /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define UART_FCR 0x4 /* FIFO Control Register (Write Only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define UART_LCR 0x6 /* Line Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define UART_MCR 0x8 /* MODEM Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define UART_LSR 0xa /* Line Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define UART_MSR 0xc /* MODEM Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define UART_SCR 0xe /* Scratch Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define UART_DLL 0x0 /* Divisor Latch (LS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define UART_DLM 0x2 /* Divisor Latch (MS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) typedef struct uart_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) volatile __u16 rbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) volatile __u16 ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) volatile __u16 iir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) volatile __u16 lcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) volatile __u16 mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) volatile __u16 lsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) volatile __u16 msr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) volatile __u16 scr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) } uart_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif /* ! __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Alias for Write Only Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define thr rbr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define tcr iir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Alias for Divisor Latch Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define dll rbr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define dlm ier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define fcr iir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Interrupt Ident Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IIR_IP 0x0100 /* "0" if Interrupt Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IIR_FIFO 0xc000 /* FIFOs enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* FIFO Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define FCR_FEN 0x0100 /* FIFO enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define FCR_RFRES 0x0200 /* Receiver FIFO reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define FCR_TFRES 0x0400 /* Transmitter FIFO reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define FCR_DMA 0x0800 /* DMA mode select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define FCR_RTL 0x4000 /* Receiver trigger (LSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define FCR_RTM 0x8000 /* Receiver trigger (MSB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Line Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LCR_STB 0x0400 /* Number of Stop Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LCR_PEN 0x0800 /* Parity Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LCR_EPS 0x1000 /* Even Parity Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LCR_SP 0x2000 /* Stick Parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LCR_SB 0x4000 /* Set Break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* MODEM Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MCR_DTR 0x0100 /* Data Terminal Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MCR_RTS 0x0200 /* Request to Send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MCR_OUT1 0x0400 /* Out 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MCR_IRQEN 0x0800 /* IRQ Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MCR_LOOP 0x1000 /* Loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Line Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define LSR_DR 0x0100 /* Data Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LSR_OE 0x0200 /* Overrun Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LSR_PE 0x0400 /* Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LSR_FE 0x0800 /* Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LSR_BI 0x1000 /* Break Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LSR_TEMT 0x4000 /* Transmitter Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LSR_FIFOE 0x8000 /* Receiver FIFO error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* MODEM Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MSR_DCTS 0x0100 /* Delta Clear to Send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MSR_DDSR 0x0200 /* Delta Data Set Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MSR_CTS 0x1000 /* Clear to Send */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MSR_DSR 0x2000 /* Data Set Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MSR_RI 0x4000 /* Ring Indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MSR_DCD 0x8000 /* Data Carrier Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Baud Rate Divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define UART_CLK (1843200) /* 1.8432 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define UART_BAUD(x) (UART_CLK / (16 * (x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* RTC register definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RTC_SECONDS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define RTC_SECONDS_ALARM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define RTC_MINUTES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define RTC_MINUTES_ALARM 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define RTC_HOURS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define RTC_HOURS_ALARM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define RTC_DAY_OF_WEEK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define RTC_DAY_OF_MONTH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define RTC_MONTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define RTC_YEAR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define RTC_FREQ_SELECT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) # define RTC_UIP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) # define RTC_DIV_CTL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* This RTC can work under 32.768KHz clock only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) # define RTC_OSC_ENABLE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) # define RTC_OSC_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RTC_CONTROL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) # define RTC_SET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) # define RTC_PIE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) # define RTC_AIE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) # define RTC_UIE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) # define RTC_SQWE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) # define RTC_DM_BINARY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) # define RTC_24H 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) # define RTC_DST_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #endif /* __ASM_SH_SMC37C93X_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags