Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * 			Manuel Lauss <mano@roarinelk.homelinux.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * (c) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef _ASM_SH_SH7760FB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define _ASM_SH_SH7760FB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * some bits of the colormap registers should be written as zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * create a mask for that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SH7760FB_PALETTE_MASK 0x00f8fcf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SH7760FB_DMA_MASK 0x0C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* palette */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LDPR(x) (((x) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* framebuffer registers and bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define LDICKR 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define LDMTR 0x402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* see sh7760fb.h for LDMTR bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LDDFR 0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LDDFR_PABD (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LDDFR_COLOR_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define LDSMR 0x406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define LDSMR_ROT (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define LDSARU 0x408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define LDSARL 0x40c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define LDLAOR 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define LDPALCR 0x412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define LDPALCR_PALS (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define LDPALCR_PALEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define LDHCNR 0x414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define LDHSYNR 0x416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define LDVDLNR 0x418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define LDVTLNR 0x41a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define LDVSYNR 0x41c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define LDACLNR 0x41e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define LDINTR 0x420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define LDPMMR 0x424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define LDPSPR 0x426
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define LDCNTR 0x428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define LDCNTR_DON (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define LDCNTR_DON2 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #ifdef CONFIG_CPU_SUBTYPE_SH7763
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) # define LDLIRNR       0x440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* LDINTR bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) # define LDINTR_MINTEN (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) # define LDINTR_FINTEN (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) # define LDINTR_VSINTEN (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) # define LDINTR_VEINTEN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) # define LDINTR_MINTS (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) # define LDINTR_FINTS (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) # define LDINTR_VSINTS (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) # define LDINTR_VEINTS (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) # define VINT_START (LDINTR_VSINTEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) # define VINT_CHECK (LDINTR_VSINTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* LDINTR bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) # define LDINTR_VINTSEL (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) # define LDINTR_VINTE (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) # define LDINTR_VINTS (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) # define VINT_START (LDINTR_VINTSEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) # define VINT_CHECK (LDINTR_VINTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* HSYNC polarity inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define LDMTR_FLMPOL (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) /* VSYNC polarity inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define LDMTR_CL1POL (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* DISPLAY-ENABLE polarity inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define LDMTR_DISPEN_LOWACT (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) /* DISPLAY DATA BUS polarity inversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define LDMTR_DPOL_LOWACT (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) /* AC modulation signal enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define LDMTR_MCNT (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) /* Disable output of HSYNC during VSYNC period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define LDMTR_CL1CNT (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /* Disable output of VSYNC during VSYNC period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define LDMTR_CL2CNT (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* Display types supported by the LCDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define LDMTR_STN_MONO_4       0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define LDMTR_STN_MONO_8       0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define LDMTR_STN_COLOR_4      0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LDMTR_STN_COLOR_8      0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LDMTR_STN_COLOR_12     0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LDMTR_STN_COLOR_16     0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LDMTR_DSTN_MONO_8      0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LDMTR_DSTN_MONO_16     0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LDMTR_DSTN_COLOR_8     0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define LDMTR_DSTN_COLOR_12    0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LDMTR_DSTN_COLOR_16    0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define LDMTR_TFT_COLOR_16     0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* framebuffer color layout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define LDDFR_1BPP_MONO 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LDDFR_2BPP_MONO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define LDDFR_4BPP_MONO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LDDFR_6BPP_MONO 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LDDFR_4BPP 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LDDFR_8BPP 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LDDFR_16BPP_RGB555 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LDDFR_16BPP_RGB565 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* LCDC Pixclock sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define LCDC_CLKSRC_BUSCLOCK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LCDC_CLKSRC_PERIPHERAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LCDC_CLKSRC_EXTERNAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LDICKR_CLKSRC(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)        (((x) & 3) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* LCDC pixclock input divider. Set to 1 at a minimum! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LDICKR_CLKDIV(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)        ((x) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct sh7760fb_platdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* Set this member to a valid fb_videmode for the display you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	 * wish to use.  The following members must be initialized:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 * xres, yres, hsync_len, vsync_len, sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	 * {left,right,upper,lower}_margin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	 * The driver uses the above members to calculate register values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	 * and memory requirements. Other members are ignored but may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	 * be used by other framebuffer layer components.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct fb_videomode *def_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* LDMTR includes display type and signal polarity.  The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	 * HSYNC/VSYNC polarities are derived from the fb_var_screeninfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 * data above; however the polarities of the following signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 * must be encoded in the ldmtr member:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	 * Display Enable signal (default high-active)  DISPEN_LOWACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	 * Display Data signals (default high-active)   DPOL_LOWACT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	 * AC Modulation signal (default off)           MCNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 * Hsync-During-Vsync suppression (default off) CL1CNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 * Vsync-during-vsync suppression (default off) CL2CNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 * NOTE: also set a display type!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	 * (one of LDMTR_{STN,DSTN,TFT}_{MONO,COLOR}_{4,8,12,16})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	u16 ldmtr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* LDDFR controls framebuffer image format (depth, organization)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	 * Use ONE of the LDDFR_?BPP_* macros!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	u16 lddfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* LDPMMR and LDPSPR control the timing of the power signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	 * for the display. Please read the SH7760 Hardware Manual,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 * Chapters 30.3.17, 30.3.18 and 30.4.6!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u16 ldpmmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	u16 ldpspr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* LDACLNR contains the line numbers after which the AC modulation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 * signal is to toggle. Set to ZERO for TFTs or displays which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 * do not need it. (Chapter 30.3.15 in SH7760 Hardware Manual).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u16 ldaclnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	/* LDICKR contains information on pixelclock source and config.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	 * Please use the LDICKR_CLKSRC() and LDICKR_CLKDIV() macros.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	 * minimal value for CLKDIV() must be 1!.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u16 ldickr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/* set this member to 1 if you wish to use the LCDC's hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	 * rotation function.  This is limited to displays <= 320x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	 * pixels resolution!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	int rotate;		/* set to 1 to rotate 90 CCW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* set this to 1 to suppress vsync irq use. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	int novsync;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	/* blanking hook for platform. Set this if your platform can do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * more than the LCDC in terms of blanking (e.g. disable clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * generator / backlight power supply / etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	void (*blank) (int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #endif /* _ASM_SH_SH7760FB_H */