Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __ASM_SH_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __ASM_SH_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /* Can be used to override the logic in pci_scan_bus for skipping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)    already-configured bus numbers - to be used for buggy BIOSes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)    or architectures with incomplete PCI setup by the loader */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define pcibios_assign_all_busses()	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * A board can define one or more PCI channels that represent built-in (or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * external) PCI controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct pci_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	struct pci_channel	*next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	struct pci_bus		*bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	struct pci_ops		*pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	struct resource		*resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	unsigned int		nr_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	unsigned long		io_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	unsigned long		mem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	unsigned long		reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	unsigned long		io_map_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	unsigned int		index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	unsigned int		need_domain_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	/* Optional error handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	struct timer_list	err_timer, serr_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	unsigned int		err_irq, serr_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* arch/sh/drivers/pci/pci.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) extern raw_spinlock_t pci_config_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) extern int register_pci_controller(struct pci_channel *hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern void pcibios_report_status(unsigned int status_mask, int warn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* arch/sh/drivers/pci/common.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) extern int early_read_config_byte(struct pci_channel *hose, int top_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 				  int bus, int devfn, int offset, u8 *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) extern int early_read_config_word(struct pci_channel *hose, int top_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 				  int bus, int devfn, int offset, u16 *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) extern int early_read_config_dword(struct pci_channel *hose, int top_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 				   int bus, int devfn, int offset, u32 *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) extern int early_write_config_byte(struct pci_channel *hose, int top_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 				   int bus, int devfn, int offset, u8 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) extern int early_write_config_word(struct pci_channel *hose, int top_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 				   int bus, int devfn, int offset, u16 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) extern int early_write_config_dword(struct pci_channel *hose, int top_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 				    int bus, int devfn, int offset, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) extern void pcibios_enable_timers(struct pci_channel *hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) extern unsigned int pcibios_handle_status_errors(unsigned long addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 				 unsigned int status, struct pci_channel *hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) extern int pci_is_66mhz_capable(struct pci_channel *hose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 				int top_bus, int current_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HAVE_PCI_MMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ARCH_GENERIC_PCI_MMAP_RESOURCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Dynamic DMA mapping stuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)  * SuperH has everything mapped statically like x86.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)  * None of the SH PCI controllers support MWI, it is always treated as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)  * direct memory write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCI_DISABLE_MWI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Board-specific fixup routines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int pcibios_map_platform_irq(const struct pci_dev *dev, u8 slot, u8 pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define pci_domain_nr(bus) ((struct pci_channel *)(bus)->sysdata)->index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static inline int pci_proc_domain(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 	struct pci_channel *hose = bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	return hose->need_domain_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Chances are this interrupt is wired PC-style ...  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 	return channel ? 15 : 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #endif /* __ASM_SH_PCI_H */