^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ASM_SH_HD64461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ASM_SH_HD64461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2000 YAEGASHI Takeshi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Hitachi HD64461 companion chip support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * (please note manual reference 0x10000000 = 0xb0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Constants for PCMCIA mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define HD64461_PCC_WINDOW 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Area 6 - Slot 0 - memory and/or IO card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HD64461_IOBASE 0xb0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HD64461_IO_OFFSET(x) (HD64461_IOBASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Area 5 - Slot 1 - memory card only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Standby Control Register for HD64461 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HD64461_STBCR HD64461_IO_OFFSET(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HD64461_STBCR_CKIO_STBY 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HD64461_STBCR_SAFECKE_IST 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HD64461_STBCR_SLCKE_IST 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HD64461_STBCR_SAFECKE_OST 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HD64461_STBCR_SLCKE_OST 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HD64461_STBCR_SMIAST 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HD64461_STBCR_SLCDST 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HD64461_STBCR_SPC0ST 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HD64461_STBCR_SPC1ST 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HD64461_STBCR_SAFEST 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HD64461_STBCR_STM0ST 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HD64461_STBCR_STM1ST 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HD64461_STBCR_SIRST 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HD64461_STBCR_SURTST 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* System Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HD64461_SYSCR HD64461_IO_OFFSET(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* CPU Data Bus Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HD64461_SCPUCR HD64461_IO_OFFSET(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Base Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HD64461_LCDCBAR HD64461_IO_OFFSET(0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Line increment address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HD64461_LCDCLOR HD64461_IO_OFFSET(0x1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Controls LCD controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HD64461_LCDCCR HD64461_IO_OFFSET(0x1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* LCCDR control bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HD64461_LCDCCR_STREQ 0x0100 /* Standby Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HD64461_LCDCCR_MOFF 0x0080 /* Memory Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HD64461_LCDCCR_REFSEL 0x0040 /* Refresh Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HD64461_LCDCCR_EPON 0x0020 /* End Power On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Controls LCD (1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HD64461_LDR1 HD64461_IO_OFFSET(0x1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define HD64461_LDR1_DON 0x01 /* Display On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HD64461_LDR1_DINV 0x80 /* Display Invert */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Controls LCD (2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HD64461_LDR2 HD64461_IO_OFFSET(0x1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HD64461_LDHNCR HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HD64461_LDHNSR HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HD64461_LDVNTR HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HD64461_LDVNDR HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HD64461_LDVSPR HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Controls LCD (3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HD64461_LDR3 HD64461_IO_OFFSET(0x101e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Palette Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HD64461_CPTWAR HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HD64461_CPTWDR HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HD64461_CPTRAR HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HD64461_CPTRDR HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define HD64461_GRDOR HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define HD64461_GRSCR HD64461_IO_OFFSET(0x1042) /* Solid Color Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HD64461_GRCFGR HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 /* Accelerator Start BITBLT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HD64461_GRCFGR_ACCSTART_LINE 0x04 /* Accelerator Start Line Drawing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HD64461_GRCFGR_COLORDEPTH16 0x01 /* Sets Colordepth 16 for Accelerator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Line Drawing Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define HD64461_LNSARH HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define HD64461_LNSARL HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HD64461_LNAXLR HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HD64461_LNDGR HD64461_IO_OFFSET(0x104c) /* Diagonal Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HD64461_LNAXR HD64461_IO_OFFSET(0x104e) /* Axial Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HD64461_LNERTR HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HD64461_LNMDR HD64461_IO_OFFSET(0x1052) /* Line Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* BitBLT Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HD64461_BBTSSARH HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HD64461_BBTSSARL HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HD64461_BBTDSARH HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HD64461_BBTDSARL HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HD64461_BBTDWR HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HD64461_BBTDHR HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HD64461_BBTPARH HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HD64461_BBTPARL HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HD64461_BBTMARH HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HD64461_BBTMARL HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HD64461_BBTROPR HD64461_IO_OFFSET(0x1068) /* ROP Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HD64461_BBTMDR HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* PC Card Controller Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Maps to Physical Area 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HD64461_PCC0ISR HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define HD64461_PCC0GCR HD64461_IO_OFFSET(0x2002) /* socket 0 general control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define HD64461_PCC0CSCR HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HD64461_PCC0CSCIER HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HD64461_PCC0SCR HD64461_IO_OFFSET(0x2008) /* socket 0 software control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Maps to Physical Area 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HD64461_PCC1ISR HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HD64461_PCC1GCR HD64461_IO_OFFSET(0x2012) /* socket 1 general control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HD64461_PCC1CSCR HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HD64461_PCC1CSCIER HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HD64461_PCC1SCR HD64461_IO_OFFSET(0x2018) /* socket 1 software control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* PCC Interface Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HD64461_PCCISR_READY 0x80 /* card ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HD64461_PCCISR_MWP 0x40 /* card write-protected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HD64461_PCCISR_CD2 0x08 /* card detect 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HD64461_PCCISR_CD1 0x04 /* card detect 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HD64461_PCCISR_BVD2 0x02 /* battery 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HD64461_PCCISR_BVD1 0x01 /* battery 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* PCC General Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HD64461_PCCGCR_DRVE 0x80 /* output drive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HD64461_PCCGCR_PA25 0x04 /* pin A25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HD64461_PCCGCR_PA24 0x02 /* pin A24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* PCC Card Status Change Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define HD64461_PCCCSCR_SRV1 0x40 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define HD64461_PCCCSCR_RC 0x04 /* READY change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HD64461_PCCCSCR_BW 0x02 /* battery warning change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define HD64461_PCCCSCR_BD 0x01 /* battery dead change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* PCC Card Status Change Interrupt Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* PCC Software Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define HD64461_PCCSCR_SWP 0x01 /* write protect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* PCC0 Output Pins Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define HD64461_P0OCR HD64461_IO_OFFSET(0x202a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* PCC1 Output Pins Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define HD64461_P1OCR HD64461_IO_OFFSET(0x202c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* PC Card General Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define HD64461_PGCR HD64461_IO_OFFSET(0x202e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Port Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define HD64461_GPACR HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HD64461_GPBCR HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define HD64461_GPCCR HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define HD64461_GPDCR HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Port Control Data Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define HD64461_GPADR HD64461_IO_OFFSET(0x4010) /* A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define HD64461_GPBDR HD64461_IO_OFFSET(0x4012) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define HD64461_GPCDR HD64461_IO_OFFSET(0x4014) /* C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define HD64461_GPDDR HD64461_IO_OFFSET(0x4016) /* D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Interrupt Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define HD64461_GPAICR HD64461_IO_OFFSET(0x4020) /* A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define HD64461_GPBICR HD64461_IO_OFFSET(0x4022) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define HD64461_GPCICR HD64461_IO_OFFSET(0x4024) /* C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define HD64461_GPDICR HD64461_IO_OFFSET(0x4026) /* D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Interrupt Status Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define HD64461_GPAISR HD64461_IO_OFFSET(0x4040) /* A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define HD64461_GPBISR HD64461_IO_OFFSET(0x4042) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define HD64461_GPCISR HD64461_IO_OFFSET(0x4044) /* C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define HD64461_GPDISR HD64461_IO_OFFSET(0x4046) /* D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Interrupt Request Register & Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define HD64461_NIRR HD64461_IO_OFFSET(0x5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define HD64461_NIMR HD64461_IO_OFFSET(0x5002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define HD64461_IRQBASE OFFCHIP_IRQ_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define OFFCHIP_IRQ_BASE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define HD64461_IRQ_NUM 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define HD64461_IRQ_UART (HD64461_IRQBASE+5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define HD64461_IRQ_IRDA (HD64461_IRQBASE+6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define HD64461_IRQ_GPIO (HD64461_IRQBASE+11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define HD64461_IRQ_AFE (HD64461_IRQBASE+12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define __IO_PREFIX hd64461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #include <asm/io_generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* arch/sh/cchips/hd6446x/hd64461/setup.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void hd64461_register_irq_demux(int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int (*demux) (int irq, void *dev), void *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void hd64461_unregister_irq_demux(int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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