^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) ! SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) ! entry.S macro define
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) .macro cli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) stc sr, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) or #0xf0, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) ldc r0, sr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) .macro sti
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) mov #0xfffffff0, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) extu.b r11, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) not r11, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) stc sr, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) and r11, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifdef CONFIG_CPU_HAS_SR_RB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) stc k_g_imask, r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) or r11, r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) ldc r10, sr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .macro get_current_thread_info, ti, tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #ifdef CONFIG_CPU_HAS_SR_RB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) stc r7_bank, \ti
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) mov #((THREAD_SIZE - 1) >> 10) ^ 0xff, \tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) shll8 \tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) shll2 \tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) mov r15, \ti
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) and \tmp, \ti
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifdef CONFIG_TRACE_IRQFLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .macro TRACE_IRQS_ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) mov.l r0, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) mov.l r1, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) mov.l r2, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) mov.l r3, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) mov.l r4, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) mov.l r5, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mov.l r6, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) mov.l r7, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) mov.l 7834f, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) jsr @r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mov.l @r15+, r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mov.l @r15+, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mov.l @r15+, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mov.l @r15+, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) mov.l @r15+, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mov.l @r15+, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mov.l @r15+, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) mov.l @r15+, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mov.l 7834f, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bra 7835f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .balign 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 7834: .long trace_hardirqs_on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 7835:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .macro TRACE_IRQS_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mov.l r0, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mov.l r1, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mov.l r2, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mov.l r3, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mov.l r4, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) mov.l r5, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mov.l r6, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mov.l r7, @-r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) mov.l 7834f, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) jsr @r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mov.l @r15+, r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mov.l @r15+, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mov.l @r15+, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mov.l @r15+, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mov.l @r15+, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mov.l @r15+, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mov.l @r15+, r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mov.l @r15+, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mov.l 7834f, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) bra 7835f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .balign 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 7834: .long trace_hardirqs_off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 7835:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .macro TRACE_IRQS_ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .macro TRACE_IRQS_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #if defined(CONFIG_CPU_SH2A) || defined(CONFIG_CPU_SH4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) # define PREF(x) pref @x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) # define PREF(x) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * Macro for use within assembly. Because the DWARF unwinder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * needs to use the frame register to unwind the stack, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * need to setup r14 with the value of the stack pointer as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * the return address is usually on the stack somewhere.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .macro setup_frame_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #ifdef CONFIG_DWARF_UNWINDER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mov r15, r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .endm
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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