^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * include/asm-sh/dma.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003, 2004 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __ASM_SH_DMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __ASM_SH_DMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm-generic/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Read and write modes can mean drastically different things depending on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * channel configuration. Consult your DMAC documentation and module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * implementation for further clues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DMA_MODE_READ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DMA_MODE_WRITE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DMA_MODE_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DMA_AUTOINIT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * DMAC (dma_info) flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DMAC_CHANNELS_CONFIGURED = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DMAC_CHANNELS_TEI_CAPABLE = 0x02, /* Transfer end interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * DMA channel capabilities / flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DMA_CONFIGURED = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Transfer end interrupt, inherited from DMAC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * wait_queue used in dma_wait_for_completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DMA_TEI_CAPABLE = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) extern spinlock_t dma_spin_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct dma_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct dma_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int (*request)(struct dma_channel *chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void (*free)(struct dma_channel *chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int (*get_residue)(struct dma_channel *chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int (*xfer)(struct dma_channel *chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int (*configure)(struct dma_channel *chan, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int (*extend)(struct dma_channel *chan, unsigned long op, void *param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct dma_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) char dev_id[16]; /* unique name per DMAC of channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned int chan; /* DMAC channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned int vchan; /* Virtual channel number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned long sar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned long dar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const char **caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) atomic_t busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) wait_queue_head_t wait_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) void *priv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct dma_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct dma_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct dma_channel *channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int first_channel_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int first_vchannel_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct dma_chan_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int ch_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const char **caplist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* arch/sh/drivers/dma/dma-api.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) extern int dma_xfer(unsigned int chan, unsigned long from,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long to, size_t size, unsigned int mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define dma_write(chan, from, to, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dma_xfer(chan, from, to, size, DMA_MODE_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define dma_write_page(chan, from, to) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) dma_write(chan, from, to, PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define dma_read(chan, from, to, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dma_xfer(chan, from, to, size, DMA_MODE_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define dma_read_page(chan, from, to) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dma_read(chan, from, to, PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) extern int request_dma_bycap(const char **dmac, const char **caps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const char *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) extern int get_dma_residue(unsigned int chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) extern struct dma_info *get_dma_info(unsigned int chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) extern struct dma_channel *get_dma_channel(unsigned int chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) extern void dma_wait_for_completion(unsigned int chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) extern void dma_configure_channel(unsigned int chan, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) extern int register_dmac(struct dma_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) extern void unregister_dmac(struct dma_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) extern struct dma_info *get_dma_info_by_name(const char *dmac_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) extern int dma_extend(unsigned int chan, unsigned long op, void *param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* arch/sh/drivers/dma/dma-sysfs.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) extern int isa_dma_bridge_buggy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define isa_dma_bridge_buggy (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #endif /* __ASM_SH_DMA_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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