Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Common header for the legacy SH DMA driver and the new dmaengine driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * extracted from arch/sh/include/asm/dma-sh.h:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2000  Takashi YOSHII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Copyright (C) 2003  Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef DMA_REGISTER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DMA_REGISTER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* DMA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SAR	0x00	/* Source Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DAR	0x04	/* Destination Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TCR	0x08	/* Transfer Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CHCR	0x0C	/* Channel Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DMAOR	0x40	/* DMA Operation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* DMAOR definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DMAOR_AE	0x00000004	/* Address Error Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DMAOR_NMIF	0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DMAOR_DME	0x00000001	/* DMA Master Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Definitions for the SuperH DMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REQ_L	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REQ_E	0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RACK_H	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RACK_L	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ACK_R	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ACK_W	0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ACK_H	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ACK_L	0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DM_INC	0x00004000	/* Destination addresses are incremented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DM_DEC	0x00008000	/* Destination addresses are decremented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DM_FIX	0x0000c000	/* Destination address is fixed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SM_INC	0x00001000	/* Source addresses are incremented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SM_DEC	0x00002000	/* Source addresses are decremented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SM_FIX	0x00003000	/* Source address is fixed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RS_IN	0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RS_OUT	0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RS_AUTO	0x00000400	/* Auto Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RS_ERS	0x00000800	/* DMA extended resource selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TS_BLK	0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TM_BUR	0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CHCR_DE	0x00000001	/* DMA Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CHCR_TE	0x00000002	/* Transfer End Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CHCR_IE	0x00000004	/* Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif