Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2002 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __ASM_SH_BARRIER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __ASM_SH_BARRIER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #if defined(CONFIG_CPU_SH4A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/cache_insns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * A brief note on ctrl_barrier(), the control register write barrier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * Legacy SH cores typically require a sequence of 8 nops after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * modification of a control register in order for the changes to take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * effect. On newer cores (like the sh4a and sh5) this is accomplished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * with icbi.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * Also note that on sh4a in the icbi case we can forego a synco for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * write barrier, as it's not necessary for control registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * Historically we have only done this type of barrier for the MMUCR, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * it's also necessary for the CCR, so we make it generic here instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #if defined(CONFIG_CPU_SH4A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define mb()		__asm__ __volatile__ ("synco": : :"memory")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define rmb()		mb()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define wmb()		mb()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ctrl_barrier()	__icbi(PAGE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #if defined(CONFIG_CPU_J2) && defined(CONFIG_SMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define __smp_mb()	do { int tmp = 0; __asm__ __volatile__ ("cas.l %0,%0,@%1" : "+r"(tmp) : "z"(&tmp) : "memory", "t"); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define __smp_rmb()	__smp_mb()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define __smp_wmb()	__smp_mb()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ctrl_barrier()	__asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm-generic/barrier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #endif /* __ASM_SH_BARRIER_H */