Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 1999 by Kaz Kojima
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Defitions for the address spaces of the SH CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __ASM_SH_ADDRSPACE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __ASM_SH_ADDRSPACE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <cpu/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* If this CPU supports segmentation, hook up the helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifdef P1SEG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)    [ P0/U0 (virtual) ]		0x00000000     <------ User space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)    [ P1 (fixed)   cached ]	0x80000000     <------ Kernel space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)    [ P2 (fixed)  non-cachable]	0xA0000000     <------ Physical access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)    [ P3 (virtual) cached]	0xC0000000     <------ vmalloced area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)    [ P4 control   ]		0xE0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Returns the privileged segment base of a given address  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PXSEG(a)	(((unsigned long)(a)) & 0xe0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #ifdef CONFIG_29BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * Map an address to a certain privileged segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define P1SEGADDR(a)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define P2SEGADDR(a)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define P3SEGADDR(a)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define P4SEGADDR(a)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * These will never work in 32-bit, don't even bother.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define P1SEGADDR(a)	({ (void)(a); BUG(); NULL; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define P2SEGADDR(a)	({ (void)(a); BUG(); NULL; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define P3SEGADDR(a)	({ (void)(a); BUG(); NULL; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define P4SEGADDR(a)	({ (void)(a); BUG(); NULL; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif /* P1SEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Check if an address can be reached in 29 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IS_29BIT(a)	(((unsigned long)(a)) < 0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #ifdef CONFIG_SH_STORE_QUEUES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  * This is a special case for the SH-4 store queues, as pages for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  * space still need to be faulted in before it's possible to flush the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)  * store queue cache for writeout to the remapped region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define P3_ADDR_MAX		(P4SEG_STORE_QUE + 0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define P3_ADDR_MAX		P4SEG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif /* __ASM_SH_ADDRSPACE_H */