^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SH7786 PCI-Express controller definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008, 2009 Renesas Technology Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __PCI_SH7786_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __PCI_SH7786_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* PCIe bus-0(x4) on SH7786 */ // Rev1.171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SH4A_PCIE_SPW_BASE 0xFE000000 /* spw config address for controller 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SH4A_PCIE_SPW_BASE1 0xFE200000 /* spw config address for controller 1 (Rev1.14)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SH4A_PCIE_SPW_BASE2 0xFCC00000 /* spw config address for controller 2 (Rev1.171)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SH4A_PCIE_SPW_BASE_LEN 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SH4A_PCI_CNFG_BASE 0xFE040000 /* pci config address for controller 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SH4A_PCI_CNFG_BASE1 0xFE240000 /* pci config address for controller 1 (Rev1.14)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SH4A_PCI_CNFG_BASE2 0xFCC40000 /* pci config address for controller 2 (Rev1.171)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SH4A_PCI_CNFG_BASE_LEN 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SH4A_PCIPIO_ADDR_OFFSET 0x000001c0 /* offset to pci config_address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SH4A_PCIPIO_DATA_OFFSET 0x00000220 /* offset to pci config_data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * for PEX8111(Max Payload Size=128B,PCIIO_SIZE=64K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * for other(Max Payload Size=4096B,PCIIO_SIZE=8M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* PCI0: PCI memory target transfer 32-bit address translation value(Rev1.11T)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SH4A_PCIBMSTR_TRANSLATION 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* SPVCR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SH4A_PCIEVCR0 (0x000000) /* R - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BITS_TOP_MB (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MASK_TOP_MB (0xff<<BITS_TOP_MB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BITS_BOT_MB (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MASK_BOT_MB (0xff<<BITS_BOT_MB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BITS_VC_ID (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MASK_VC_ID (0xffff<<BITS_VC_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* SPVCR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SH4A_PCIEVCR1 (0x000004) /* R - 0x0000 0000 32*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BITS_BADOPC (5) /* 5 BADOPC 0 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MASK_BADOPC (1<<BITS_BADOPC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BITS_BADDEST (4) /*4 BADDEST 0 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MASK_BADDEST (1<<BITS_BADDEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BITS_UNSOLRESP (3) /* 3 UNSOLRESP 0 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MASK_UNSOLRESP (1<<BITS_UNSOLRESP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BITS_ERRSNT (1) /* 1 ERRSNT 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MASK_ERRSNT (1<<BITS_ERRSNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BITS_ERRRCV (0) /* 0 ERRRCV 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MASK_ERRRCV (1<<BITS_ERRRCV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* PCIEENBLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SH4A_PCIEENBLR (0x000008) /* R/W - 0x0000 0001 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* PCIEECR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SH4A_PCIEECR (0x00000C) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BITS_ENBL (0) /* 0 ENBL 0 R/W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MASK_ENBL (1<<BITS_ENBL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* PCIEPAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SH4A_PCIEPAR (0x000010) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BITS_BN (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MASK_BN (0xff<<BITS_BN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BITS_DN (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MASK_DN (0x1f<<BITS_DN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BITS_FN (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MASK_FN (0x7<<BITS_FN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BITS_EREGNO (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MASK_EREGNO (0xff<<BITS_EREGNO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BITS_REGNO (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MASK_REGNO (0x3f<<BITS_REGNO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* PCIEPCTLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SH4A_PCIEPCTLR (0x000018) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BITS_CCIE (31) /* 31 CCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MASK_CCIE (1<<BITS_CCIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BITS_TYPE (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MASK_TYPE (1<<BITS_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BITS_C_VC (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MASK_C_VC (1<<BITS_C_VC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* PCIEPDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SH4A_PCIEPDR (0x000020) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BITS_PDR (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MASK_PDR (0xffffffff<<BITS_PDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* PCIEMSGALR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SH4A_PCIEMSGALR (0x000030) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BITS_MSGADRL (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MASK_MSGADRL (0xffffffff<<BITS_MSGADRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* PCIEMSGAHR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SH4A_PCIEMSGAHR (0x000034) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BITS_MSGADRH (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MASK_MSGADRH (0xffffffff<<BITS_MSGADRH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* PCIEMSGCTLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SH4A_PCIEMSGCTLR (0x000038) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BITS_MSGIE (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MASK_MSGIE (1<<BITS_MSGIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BITS_MROUTE (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MASK_MROUTE (0x7<<BITS_MROUTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BITS_MCODE (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MASK_MCODE (0xff<<BITS_MCODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BITS_M_VC (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MASK_M_VC (1<<BITS_M_VC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* PCIEMSG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SH4A_PCIEMSG (0x000040) /* W - - 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BITS_MDATA (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MASK_MDATA (0xffffffff<<BITS_MDATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* PCIEUNLOCKCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SH4A_PCIEUNLOCKCR (0x000048) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* PCIEIDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SH4A_PCIEIDR (0x000060) /* R/W - 0x0101 1101 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* PCIEDBGCTLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SH4A_PCIEDBGCTLR (0x000100) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* PCIEINTXR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SH4A_PCIEINTXR (0x004000) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* PCIERMSGR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SH4A_PCIERMSGR (0x004010) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* PCIERSTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SH4A_PCIERSTR(x) (0x008000 + ((x) * 0x4)) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* PCIESRSTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SH4A_PCIESRSTR (0x008040) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* PCIEPHYCTLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SH4A_PCIEPHYCTLR (0x010000) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BITS_CKE (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MASK_CKE (1<<BITS_CKE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* PCIERMSGIER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SH4A_PCIERMSGIER (0x004040) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* PCIEPHYADRR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SH4A_PCIEPHYADRR (0x010004) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define BITS_ACK (24) // Rev1.171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MASK_ACK (1<<BITS_ACK) // Rev1.171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BITS_CMD (16) // Rev1.171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MASK_CMD (0x03<<BITS_CMD) // Rev1.171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define BITS_LANE (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MASK_LANE (0x0f<<BITS_LANE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define BITS_ADR (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MASK_ADR (0xff<<BITS_ADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* PCIEPHYDINR */ // Rev1.171 start.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SH4A_PCIEPHYDINR (0x010008) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* PCIEPHYDOUTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SH4A_PCIEPHYDOUTR (0x01000C) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* PCIEPHYSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SH4A_PCIEPHYSR (0x010010) /* R/W - 0x0000 0000 32 */ // Rev1.171 end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* PCIEPHYDATAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SH4A_PCIEPHYDATAR (0x00008) /* R/W - 0xxxxx xxxx 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define BITS_DATA (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MASK_DATA (0xffffffff<<BITS_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* PCIETCTLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SH4A_PCIETCTLR (0x020000) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define BITS_CFINT (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MASK_CFINT (1<<BITS_CFINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* PCIETSTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SH4A_PCIETSTR (0x020004) /* R 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* PCIEINTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SH4A_PCIEINTR (0x020008) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define BITS_INT_RX_ERP (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MASK_INT_RX_ERP (1<<BITS_INT_RX_ERP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BITS_INT_RX_VCX_Posted (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MASK_INT_RX_VCX_Posted (1<<BITS_INT_RX_VCX_Posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define BITS_INT_RX_VCX_NonPosted (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MASK_INT_RX_VCX_NonPosted (1<<BITS_INT_RX_VCX_NonPosted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define BITS_INT_RX_VCX_CPL (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MASK_INT_RX_VCX_CPL (1<<BITS_INT_RX_VCX_CPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define BITS_INT_TX_VCX_Posted (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MASK_INT_TX_VCX_Posted (1<<BITS_INT_TX_VCX_Posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define BITS_INT_TX_VCX_NonPosted (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MASK_INT_TX_VCX_NonPosted (1<<BITS_INT_TX_VCX_NonPosted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BITS_INT_TX_VCX_CPL (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MASK_INT_TX_VCX_CPL (1<<BITS_INT_TX_VCX_CPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define BITS_INT_RX_VC0_Posted (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MASK_INT_RX_VC0_Posted (1<<BITS_INT_RX_VC0_Posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define BITS_INT_RX_VC0_NonPosted (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MASK_INT_RX_VC0_NonPosted (1<<BITS_INT_RX_VC0_NonPosted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define BITS_INT_RX_VC0_CPL (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MASK_INT_RX_VC0_CPL (1<<BITS_INT_RX_VC0_CPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define BITS_INT_TX_VC0_Posted (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MASK_INT_TX_VC0_Posted (1<<BITS_INT_TX_VC0_Posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define BITS_INT_TX_VC0_NonPosted (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MASK_INT_TX_VC0_NonPosted (1<<BITS_INT_TX_VC0_NonPosted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define BITS_INT_TX_VC0_CPL (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MASK_INT_TX_VC0_CPL (1<<BITS_INT_TX_VC0_CPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define BITS_INT_RX_CTRL (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MASK_INT_RX_CTRL (1<<BITS_INT_RX_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define BITS_INT_TX_CTRL (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MASK_INT_TX_CTRL (1<<BITS_INT_TX_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define BITS_INTTL (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MASK_INTTL (1<<BITS_INTTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define BITS_INTDL (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MASK_INTDL (1<<BITS_INTDL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define BITS_INTMAC (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MASK_INTMAC (1<<BITS_INTMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define BITS_INTPM (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MASK_INTPM (1<<BITS_INTPM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* PCIEINTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SH4A_PCIEINTER (0x02000C) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define BITS_INT_RX_ERP (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MASK_INT_RX_ERP (1<<BITS_INT_RX_ERP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define BITS_INT_RX_VCX_Posted (30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MASK_INT_RX_VCX_Posted (1<<BITS_INT_RX_VCX_Posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define BITS_INT_RX_VCX_NonPosted (29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MASK_INT_RX_VCX_NonPosted (1<<BITS_INT_RX_VCX_NonPosted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define BITS_INT_RX_VCX_CPL (28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MASK_INT_RX_VCX_CPL (1<<BITS_INT_RX_VCX_CPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define BITS_INT_TX_VCX_Posted (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MASK_INT_TX_VCX_Posted (1<<BITS_INT_TX_VCX_Posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define BITS_INT_TX_VCX_NonPosted (25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MASK_INT_TX_VCX_NonPosted (1<<BITS_INT_TX_VCX_NonPosted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define BITS_INT_TX_VCX_CPL (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MASK_INT_TX_VCX_CPL (1<<BITS_INT_TX_VCX_CPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define BITS_INT_RX_VC0_Posted (22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MASK_INT_RX_VC0_Posted (1<<BITS_INT_RX_VC0_Posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define BITS_INT_RX_VC0_NonPosted (21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MASK_INT_RX_VC0_NonPosted (1<<BITS_INT_RX_VC0_NonPosted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define BITS_INT_RX_VC0_CPL (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MASK_INT_RX_VC0_CPL (1<<BITS_INT_RX_VC0_CPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define BITS_INT_TX_VC0_Posted (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MASK_INT_TX_VC0_Posted (1<<BITS_INT_TX_VC0_Posted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define BITS_INT_TX_VC0_NonPosted (17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MASK_INT_TX_VC0_NonPosted (1<<BITS_INT_TX_VC0_NonPosted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define BITS_INT_TX_VC0_CPL (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MASK_INT_TX_VC0_CPL (1<<BITS_INT_TX_VC0_CPL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define BITS_INT_RX_CTRL (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MASK_INT_RX_CTRL (1<<BITS_INT_RX_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define BITS_INT_TX_CTRL (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MASK_INT_TX_CTRL (1<<BITS_INT_TX_CTRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define BITS_INTTL (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MASK_INTTL (1<<BITS_INTTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define BITS_INTDL (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MASK_INTDL (1<<BITS_INTDL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define BITS_INTMAC (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MASK_INTMAC (1<<BITS_INTMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define BITS_INTPM (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MASK_INTPM (1<<BITS_INTPM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* PCIEEH0R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SH4A_PCIEEHR(x) (0x020010 + ((x) * 0x4)) /* R - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* PCIEAIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SH4A_PCIEAIR (SH4A_PCIE_BASE + 0x020010) /* R/W R/W 0xxxxx xxxx 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* PCIECIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SH4A_PCIECIR (SH4A_PCIE_BASE) /* R/W R/W 0xxxxx xxxx 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* PCIEERRFR */ // Rev1.18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SH4A_PCIEERRFR (0x020020) /* R/W R/W 0xxxxx xxxx 32 */ // Rev1.18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* PCIEERRFER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SH4A_PCIEERRFER (0x020024) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* PCIEERRFR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SH4A_PCIEERRFR2 (0x020028) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* PCIEMSIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SH4A_PCIEMSIR (0x020040) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* PCIEMSIFR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SH4A_PCIEMSIFR (0x020044) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* PCIEPWRCTLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SH4A_PCIEPWRCTLR (0x020100) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* PCIEPCCTLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SH4A_PCIEPCCTLR (0x020180) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) // Rev1.18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* PCIELAR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SH4A_PCIELAR0 (0x020200) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define BITS_LARn (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MASK_LARn (0xfff<<BITS_LARn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SH4A_PCIE_020204 (0x020204) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* PCIELAMR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define SH4A_PCIELAMR0 (0x020208) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define BITS_LAMRn (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define MASK_LAMRn (0x1ff<<BITS_LAMRn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define BITS_LAREn (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define MASK_LAREn (0x1<<BITS_LAREn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* PCIECSCR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SH4A_PCIECSCR0 (0x020210) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define BITS_RANGE (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define MASK_RANGE (0x7<<BITS_RANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define BITS_SNPMD (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define MASK_SNPMD (0x3<<BITS_SNPMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* PCIECSAR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define SH4A_PCIECSAR0 (0x020214) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define BITS_CSADR (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define MASK_CSADR (0xffffffff<<BITS_CSADR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* PCIESTCTLR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SH4A_PCIESTCTLR0 (0x020218) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define BITS_SHPRI (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define MASK_SHPRI (0x0f<<BITS_SHPRI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SH4A_PCIE_020224 (0x020224) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SH4A_PCIELAR1 (0x020220) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SH4A_PCIELAMR1 (0x020228) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SH4A_PCIECSCR1 (0x020230) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SH4A_PCIECSAR1 (0x020234) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SH4A_PCIESTCTLR1 (0x020238) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define SH4A_PCIELAR2 (0x020240) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SH4A_PCIE_020244 (0x020244) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SH4A_PCIELAMR2 (0x020248) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define SH4A_PCIECSCR2 (0x020250) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define SH4A_PCIECSAR2 (0x020254) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define SH4A_PCIESTCTLR2 (0x020258) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SH4A_PCIELAR3 (0x020260) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SH4A_PCIE_020264 (0x020264) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SH4A_PCIELAMR3 (0x020268) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SH4A_PCIECSCR3 (0x020270) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SH4A_PCIECSAR3 (0x020274) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define SH4A_PCIESTCTLR3 (0x020278) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define SH4A_PCIELAR4 (0x020280) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SH4A_PCIE_020284 (0x020284) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SH4A_PCIELAMR4 (0x020288) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define SH4A_PCIECSCR4 (0x020290) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SH4A_PCIECSAR4 (0x020294) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SH4A_PCIESTCTLR4 (0x020298) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SH4A_PCIELAR5 (0x0202A0) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SH4A_PCIE_0202A4 (0x0202A4) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define SH4A_PCIELAMR5 (0x0202A8) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SH4A_PCIECSCR5 (0x0202B0) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SH4A_PCIECSAR5 (0x0202B4) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SH4A_PCIESTCTLR5 (0x0202B8) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* PCIEPARL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SH4A_PCIEPARL(x) (0x020400 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define BITS_PAL (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define MASK_PAL (0x3fff<<BITS_PAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* PCIEPARH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SH4A_PCIEPARH(x) (0x020404 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define BITS_PAH (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MASK_PAH (0xffffffff<<BITS_PAH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* PCIEPAMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SH4A_PCIEPAMR(x) (0x020408 + ((x) * 0x20)) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define BITS_PAM (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define MASK_PAM (0x3fff<<BITS_PAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* PCIEPTCTLR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SH4A_PCIEPTCTLR(x) (0x02040C + ((x) * 0x20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define BITS_PARE (31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define MASK_PARE (0x1<<BITS_PARE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define BITS_TC (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define MASK_TC (0x7<<BITS_TC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define BITS_T_VC (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define MASK_T_VC (0x1<<BITS_T_VC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define BITS_LOCK (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define MASK_LOCK (0x1<<BITS_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define BITS_SPC (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define MASK_SPC (0x1<<BITS_SPC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SH4A_PCIEDMAOR (0x021000) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SH4A_PCIEDMSAR0 (0x021100) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SH4A_PCIEDMSAHR0 (0x021104) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SH4A_PCIEDMDAR0 (0x021108) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SH4A_PCIEDMDAHR0 (0x02110C) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SH4A_PCIEDMBCNTR0 (0x021110) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SH4A_PCIEDMSBCNTR0 (0x021114) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SH4A_PCIEDMSTRR0 (0x021118) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SH4A_PCIEDMCCAR0 (0x02111C) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SH4A_PCIEDMCCR0 (0x021120) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SH4A_PCIEDMCC2R0 (0x021124) /* R/W R/W 0x0000 0000 - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SH4A_PCIEDMCCCR0 (0x021128) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SH4A_PCIEDMCHSR0 (0x02112C) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SH4A_PCIEDMSAR1 (0x021140) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SH4A_PCIEDMSAHR1 (0x021144) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define SH4A_PCIEDMDAR1 (0x021148) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SH4A_PCIEDMDAHR1 (0x02114C) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SH4A_PCIEDMBCNTR1 (0x021150) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SH4A_PCIEDMSBCNTR1 (0x021154) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SH4A_PCIEDMSTRR1 (0x021158) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SH4A_PCIEDMCCAR1 (0x02115C) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define SH4A_PCIEDMCCR1 (0x021160) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define SH4A_PCIEDMCC2R1 (0x021164) /* R/W R/W 0x0000 0000 - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SH4A_PCIEDMCCCR1 (0x021168) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SH4A_PCIEDMCHSR1 (0x02116C) /* R/W - 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define SH4A_PCIEDMSAR2 (0x021180) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SH4A_PCIEDMSAHR2 (0x021184) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define SH4A_PCIEDMDAR2 (0x021188) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SH4A_PCIEDMDAHR2 (0x02118C) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define SH4A_PCIEDMBCNTR2 (0x021190) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define SH4A_PCIEDMSBCNTR2 (0x021194) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define SH4A_PCIEDMSTRR2 (0x021198) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define SH4A_PCIEDMCCAR2 (0x02119C) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define SH4A_PCIEDMCCR2 (0x0211A0) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SH4A_PCIEDMCC2R2 (0x0211A4) /* R/W R/W 0x0000 0000 - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define SH4A_PCIEDMCCCR2 (0x0211A8) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SH4A_PCIEDMSAR3 (0x0211C0) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define SH4A_PCIEDMSAHR3 (0x0211C4) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define SH4A_PCIEDMDAR3 (0x0211C8) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define SH4A_PCIEDMDAHR3 (0x0211CC) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define SH4A_PCIEDMBCNTR3 (0x0211D0) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define SH4A_PCIEDMSBCNTR3 (0x0211D4) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define SH4A_PCIEDMSTRR3 (0x0211D8) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define SH4A_PCIEDMCCAR3 (0x0211DC) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define SH4A_PCIEDMCCR3 (0x0211E0) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define SH4A_PCIEDMCC2R3 (0x0211E4) /* R/W R/W 0x0000 0000 - */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define SH4A_PCIEDMCCCR3 (0x0211E8) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SH4A_PCIEDMCHSR3 (0x0211EC) /* R/W R/W 0x0000 0000 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define SH4A_PCIEPCICONF0 (0x040000) /* R R - 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define SH4A_PCIEPCICONF1 (0x040004) /* R/W R/W 0x0008 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SH4A_PCIEPCICONF2 (0x040008) /* R/W R/W 0xFF00 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define SH4A_PCIEPCICONF3 (0x04000C) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define SH4A_PCIEPCICONF4 (0x040010) /* - R/W - 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define SH4A_PCIEPCICONF5 (0x040014) /* - R/W - 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define SH4A_PCIEPCICONF6 (0x040018) /* - R/W - 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SH4A_PCIEPCICONF7 (0x04001C) /* - R/W - 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SH4A_PCIEPCICONF8 (0x040020) /* - R/W - 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SH4A_PCIEPCICONF9 (0x040024) /* - R/W - 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SH4A_PCIEPCICONF10 (0x040028) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define SH4A_PCIEPCICONF11 (0x04002C) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define SH4A_PCIEPCICONF12 (0x040030) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SH4A_PCIEPCICONF13 (0x040034) /* R/W R/W 0x0000 0040 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define SH4A_PCIEPCICONF14 (0x040038) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SH4A_PCIEPCICONF15 (0x04003C) /* R/W R/W 0x0000 00FF 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define SH4A_PCIEPMCAP0 (0x040040) /* R/W R 0x0003 5001 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SH4A_PCIEPMCAP1 (0x040044) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define SH4A_PCIEMSICAP0 (0x040050) /* R/W R/W 0x0180 7005 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define SH4A_PCIEMSICAP1 (0x040054) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define SH4A_PCIEMSICAP2 (0x040058) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define SH4A_PCIEMSICAP3 (0x04005C) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define SH4A_PCIEMSICAP4 (0x040060) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define SH4A_PCIEMSICAP5 (0x040064) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define SH4A_PCIEEXPCAP0 (0x040070) /* R/W R/W 0x0001 0010 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SH4A_PCIEEXPCAP1 (0x040074) /* R/W R 0x0000 0005 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define SH4A_PCIEEXPCAP2 (0x040078) /* R/W R/W 0x0000 0801 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define SH4A_PCIEEXPCAP3 (0x04007C) /* R/W R 0x0003 F421 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define SH4A_PCIEEXPCAP4 (0x040080) /* R/W R/W 0x0041 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SH4A_PCIEEXPCAP5 (0x040084) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define SH4A_PCIEEXPCAP6 (0x040088) /* R/W R/W 0x0000 03C0 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SH4A_PCIEEXPCAP7 (0x04008C) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define SH4A_PCIEEXPCAP8 (0x040090) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define SH4A_PCIEVCCAP0 (0x040100) /* R/W R 0x1B01 0002 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SH4A_PCIEVCCAP1 (0x040104) /* R R 0x0000 0001 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SH4A_PCIEVCCAP2 (0x040108) /* R R 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SH4A_PCIEVCCAP3 (0x04010C) /* R R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define SH4A_PCIEVCCAP4 (0x040110) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SH4A_PCIEVCCAP5 (0x040114) /* R/W R/W 0x8000 00FF 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define SH4A_PCIEVCCAP6 (0x040118) /* R/W R 0x0002 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define SH4A_PCIEVCCAP7 (0x04011C) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define SH4A_PCIEVCCAP8 (0x040120) /* R/W R/W 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define SH4A_PCIEVCCAP9 (0x040124) /* R/W R 0x0002 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define SH4A_PCIENUMCAP0 (0x0001B0) /* RW R 0x0001 0003 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define SH4A_PCIENUMCAP1 (0x0001B4) /* R R 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SH4A_PCIENUMCAP2 (0x0001B8) /* R R 0x0000 0000 8/16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define SH4A_PCIEIDSETR0 (0x041000) /* R/W R 0x0000 FFFF 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define SH4A_PCIEIDSETR1 (0x041004) /* R/W R 0xFF00 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define SH4A_PCIEBAR0SETR (0x041008) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define SH4A_PCIEBAR1SETR (0x04100C) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define SH4A_PCIEBAR2SETR (0x041010) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define SH4A_PCIEBAR3SETR (0x041014) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define SH4A_PCIEBAR4SETR (0x041018) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define SH4A_PCIEBAR5SETR (0x04101C) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define SH4A_PCIECISSETR (0x041020) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define SH4A_PCIEIDSETR2 (0x041024) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define SH4A_PCIEEROMSETR (0x041028) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define SH4A_PCIEDSERSETR0 (0x04102C) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define SH4A_PCIEDSERSETR1 (0x041030) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define SH4A_PCIECTLR (0x041040) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define SH4A_PCIETLSR (0x041044) /* R/W1C R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define SH4A_PCIETLCTLR (0x041048) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define SH4A_PCIEDLSR (0x04104C) /* R/W1C R 0x4003 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define SH4A_PCIEDLCTLR (0x041050) /* R R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define SH4A_PCIEMACSR (0x041054) /* R/W1C R 0x0041 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define SH4A_PCIEMACCTLR (0x041058) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define PCIEMACCTLR_SCR_DIS (1 << 27) /* scramble disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define SH4A_PCIEPMSTR (0x04105C) /* R/W1C R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define SH4A_PCIEPMCTLR (0x041060) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define SH4A_PCIETLINTENR (0x041064) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define SH4A_PCIEDLINTENR (0x041068) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define PCIEDLINTENR_DLL_ACT_ENABLE (1 << 31) /* DL active irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define SH4A_PCIEMACINTENR (0x04106C) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define SH4A_PCIEPMINTENR (0x041070) /* R/W R 0x0000 0000 16/32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define SH4A_PCIETXDCTLR (0x044000) /* R/W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define SH4A_PCIETXCTLR (0x044020) /* R/W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define SH4A_PCIETXSR (0x044028) /* R - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define SH4A_PCIETXVC0DCTLR (0x044100) /* R/W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define SH4A_PCIETXVC0SR (0x044108) /* R/W - H'00888000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define SH4A_PCIEVC0PDTXR (0x044110) /* W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define SH4A_PCIEVC0PHTXR (0x044118) /* W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define SH4A_PCIEVC0NPDTXR (0x044120) /* W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define SH4A_PCIEVC0NPHTXR (0x044128) /* W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define SH4A_PCIEVC0CDTXR (0x044130) /* W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define SH4A_PCIEVC0CHTXR (0x044138) /* W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SH4A_PCIETXVCXDCTLR (0x044200) /* R/W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SH4A_PCIETXVCXSR (0x044208) /* R/W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define SH4A_PCIEVCXPDTXR (0x044210) /* W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define SH4A_PCIEVCXPHTXR (0x044218) /* W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define SH4A_PCIEVCXNPDTXR (0x044220) /* W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define SH4A_PCIEVCXNPHTXR (0x044228) /* W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define SH4A_PCIEVCXCDTXR (0x044230) /* W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define SH4A_PCIEVCXCHTXR (0x044238) /* W - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define SH4A_PCIERDCTLR (0x046000) /* RW - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define SH4A_PCIEERPCTLR (0x046008) /* RW - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define SH4A_PCIEERPHR (0x046010) /* R - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define SH4A_PCIEERPERR (0x046018) /* R - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define SH4A_PCIERXVC0DCTLR (0x046100) /* RW - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define SH4A_PCIERXVC0SR (0x046108) /* RW - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define SH4A_PCIEVC0PDRXR (0x046140) /* R - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define SH4A_PCIEVC0PHRXR (0x046148) /* R - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define SH4A_PCIEVC0PERR (0x046150) /* R - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define SH4A_PCIEVC0NPDRXR (0x046158) /* R - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define SH4A_PCIEVC0NPHRXR (0x046160) /* R - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define SH4A_PCIEVC0NPERR (0x046168) /* R - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define SH4A_PCIEVC0CDRXR (0x046170) /* R - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define SH4A_PCIEVC0CHRXR (0x046178) /* R - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define SH4A_PCIEVC0CERR (0x046180) /* R - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SH4A_PCIERXVCXDCTLR (0x046200) /* RW - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define SH4A_PCIERXVCXSR (0x046208) /* RW - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define SH4A_PCIEVCXPDRXR (0x046240) /* R - H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define SH4A_PCIEVCXPHRXR (0x046248) /* R H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define SH4A_PCIEVCXPERR (0x046250) /* R H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define SH4A_PCIEVCXNPDRXR (0x046258) /* R H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define SH4A_PCIEVCXNPHRXR (0x046260) /* R H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define SH4A_PCIEVCXNPERR (0x046268) /* R H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define SH4A_PCIEVCXCDRXR (0x046270) /* R H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define SH4A_PCIEVCXCHRXR (0x046278) /* R H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define SH4A_PCIEVCXCERR (0x046280) /* R H'00000000_00000000 32/64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* SSI Register Definition for MSI WORK AROUND --hamada */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define SH4A_PCI_SSI_BASE 0xFFE00000 /* spw config address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SH4A_PCI_SSI_BASE_LEN 0x00100000 /* 1MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define SH4A_SSICR0 (0x000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define SH4A_SSICR1 (0x010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define SH4A_SSICR2 (0x020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define SH4A_SSICR3 (0x030000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define PCI_REG(x) ((x) + 0x40000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) pci_write_reg(struct pci_channel *chan, unsigned long val, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) __raw_writel(val, chan->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) pci_read_reg(struct pci_channel *chan, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return __raw_readl(chan->reg_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #endif /* __PCI_SH7786_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags