^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Low-Level PCI Express Support for the SH7786
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 - 2011 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define pr_fmt(fmt) "PCI: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sh_clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sh_intc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <cpu/sh7786.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "pcie-sh7786.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct sh7786_pcie_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct pci_channel *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct clk *fclk, phy_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct sh7786_pcie_port *sh7786_pcie_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static unsigned int nr_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static unsigned long dma_pfn_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) size_t memsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u64 memstart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static struct sh7786_pcie_hwops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int (*core_init)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) async_func_t port_init_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) } *sh7786_pcie_hwops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct resource sh7786_pci0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .name = "PCIe0 MEM 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .start = 0xfd000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .end = 0xfd000000 + SZ_8M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .name = "PCIe0 MEM 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .start = 0xc0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .end = 0xc0000000 + SZ_512M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .name = "PCIe0 MEM 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .start = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .end = 0x10000000 + SZ_64M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .name = "PCIe0 IO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .start = 0xfe100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .end = 0xfe100000 + SZ_1M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct resource sh7786_pci1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .name = "PCIe1 MEM 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .start = 0xfd800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .end = 0xfd800000 + SZ_8M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .name = "PCIe1 MEM 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .start = 0xa0000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .end = 0xa0000000 + SZ_512M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .name = "PCIe1 MEM 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .start = 0x30000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .end = 0x30000000 + SZ_256M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .name = "PCIe1 IO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .start = 0xfe300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .end = 0xfe300000 + SZ_1M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct resource sh7786_pci2_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .name = "PCIe2 MEM 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .start = 0xfc800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .end = 0xfc800000 + SZ_4M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = "PCIe2 MEM 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .start = 0x80000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .end = 0x80000000 + SZ_512M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .name = "PCIe2 MEM 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .start = 0x20000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .end = 0x20000000 + SZ_256M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .name = "PCIe2 IO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .start = 0xfcd00000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .end = 0xfcd00000 + SZ_1M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) extern struct pci_ops sh7786_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DEFINE_CONTROLLER(start, idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .pci_ops = &sh7786_pci_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .resources = sh7786_pci##idx##_resources, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .nr_resources = ARRAY_SIZE(sh7786_pci##idx##_resources), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .reg_base = start, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .mem_offset = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .io_offset = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct pci_channel sh7786_pci_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DEFINE_CONTROLLER(0xfe000000, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DEFINE_CONTROLLER(0xfe200000, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DEFINE_CONTROLLER(0xfcc00000, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct clk fixed_pciexclkp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .rate = 100000000, /* 100 MHz reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void sh7786_pci_fixup(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Prevent enumeration of root complex resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (pci_is_root_bus(dev->bus) && dev->devfn == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev->resource[i].start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev->resource[i].end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev->resource[i].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_SH7786,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) sh7786_pci_fixup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int __init phy_wait_for_ack(struct pci_channel *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) while (timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (pci_read_reg(chan, SH4A_PCIEPHYADRR) & (1 << BITS_ACK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int __init pci_wait_for_irq(struct pci_channel *chan, unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) while (timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if ((pci_read_reg(chan, SH4A_PCIEINTR) & mask) == mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static void __init phy_write_reg(struct pci_channel *chan, unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int lane, unsigned int data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned long phyaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) phyaddr = (1 << BITS_CMD) + ((lane & 0xf) << BITS_LANE) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ((addr & 0xff) << BITS_ADR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Set write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pci_write_reg(chan, data, SH4A_PCIEPHYDOUTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pci_write_reg(chan, phyaddr, SH4A_PCIEPHYADRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) phy_wait_for_ack(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Clear command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pci_write_reg(chan, 0, SH4A_PCIEPHYDOUTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pci_write_reg(chan, 0, SH4A_PCIEPHYADRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) phy_wait_for_ack(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int __init pcie_clk_init(struct sh7786_pcie_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct pci_channel *chan = port->hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) char fclk_name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * First register the fixed clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = clk_register(&fixed_pciexclkp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (unlikely(ret != 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * Grab the port's function clock, which the PHY clock depends
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * on. clock lookups don't help us much at this point, since no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * dev_id is available this early. Lame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) snprintf(fclk_name, sizeof(fclk_name), "pcie%d_fck", port->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) port->fclk = clk_get(NULL, fclk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (IS_ERR(port->fclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = PTR_ERR(port->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) goto err_fclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) clk_enable(port->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * And now, set up the PHY clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) clk = &port->phy_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) memset(clk, 0, sizeof(struct clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) clk->parent = &fixed_pciexclkp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) clk->enable_bit = BITS_CKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = sh_clk_mstp_register(clk, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (unlikely(ret < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto err_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) err_phy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) clk_disable(port->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) clk_put(port->fclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) err_fclk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) clk_unregister(&fixed_pciexclkp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int __init phy_init(struct sh7786_pcie_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct pci_channel *chan = port->hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int timeout = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) clk_enable(&port->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Initialize the phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) phy_write_reg(chan, 0x60, 0xf, 0x004b008b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) phy_write_reg(chan, 0x61, 0xf, 0x00007b41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) phy_write_reg(chan, 0x64, 0xf, 0x00ff4f00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) phy_write_reg(chan, 0x65, 0xf, 0x09070907);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) phy_write_reg(chan, 0x66, 0xf, 0x00000010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) phy_write_reg(chan, 0x74, 0xf, 0x0007001c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) phy_write_reg(chan, 0x79, 0xf, 0x01fc000d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) phy_write_reg(chan, 0xb0, 0xf, 0x00000610);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Deassert Standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) phy_write_reg(chan, 0x67, 0x1, 0x00000400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Disable clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) clk_disable(&port->phy_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) while (timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (pci_read_reg(chan, SH4A_PCIEPHYSR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void __init pcie_reset(struct sh7786_pcie_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct pci_channel *chan = port->hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pci_write_reg(chan, 1, SH4A_PCIESRSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pci_write_reg(chan, 0, SH4A_PCIETCTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pci_write_reg(chan, 0, SH4A_PCIESRSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pci_write_reg(chan, 0, SH4A_PCIETXVC0SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int __init pcie_init(struct sh7786_pcie_port *port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct pci_channel *chan = port->hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) phys_addr_t memstart, memend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int ret, i, win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Begin initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) pcie_reset(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * Initial header for port config space is type 1, set the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * class to match. Hardware takes care of propagating the IDSETR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * settings, so there is no need to bother with a quirk.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pci_write_reg(chan, PCI_CLASS_BRIDGE_PCI << 16, SH4A_PCIEIDSETR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Initialize default capabilities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) data = pci_read_reg(chan, SH4A_PCIEEXPCAP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) data &= ~(PCI_EXP_FLAGS_TYPE << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (port->endpoint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) data |= PCI_EXP_TYPE_ENDPOINT << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) data |= PCI_EXP_TYPE_ROOT_PORT << 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) data |= PCI_CAP_ID_EXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pci_write_reg(chan, data, SH4A_PCIEEXPCAP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Enable data link layer active state reporting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) pci_write_reg(chan, PCI_EXP_LNKCAP_DLLLARC, SH4A_PCIEEXPCAP3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Enable extended sync and ASPM L0s support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) data = pci_read_reg(chan, SH4A_PCIEEXPCAP4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) data &= ~PCI_EXP_LNKCTL_ASPMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) data |= PCI_EXP_LNKCTL_ES | 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pci_write_reg(chan, data, SH4A_PCIEEXPCAP4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Write out the physical slot number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) data = pci_read_reg(chan, SH4A_PCIEEXPCAP5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) data &= ~PCI_EXP_SLTCAP_PSN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) data |= (port->index + 1) << 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pci_write_reg(chan, data, SH4A_PCIEEXPCAP5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Set the completion timer timeout to the maximum 32ms. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) data = pci_read_reg(chan, SH4A_PCIETLCTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) data &= ~0x3f00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) data |= 0x32 << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pci_write_reg(chan, data, SH4A_PCIETLCTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Set fast training sequences to the maximum 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * and enable MAC data scrambling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) data &= ~PCIEMACCTLR_SCR_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) data |= (0xff << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) memstart = __pa(memory_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) memend = __pa(memory_end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) memsize = roundup_pow_of_two(memend - memstart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * The start address must be aligned on its size. So we round
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * it down, and then recalculate the size so that it covers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * the entire memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) memstart = ALIGN_DOWN(memstart, memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) memsize = roundup_pow_of_two(memend - memstart);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * If there's more than 512MB of memory, we need to roll over to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * LAR1/LAMR1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (memsize > SZ_512M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) pci_write_reg(chan, memstart + SZ_512M, SH4A_PCIELAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pci_write_reg(chan, ((memsize - SZ_512M) - SZ_256) | 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) SH4A_PCIELAMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) memsize = SZ_512M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Otherwise just zero it out and disable it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) pci_write_reg(chan, 0, SH4A_PCIELAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pci_write_reg(chan, 0, SH4A_PCIELAMR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * LAR0/LAMR0 covers up to the first 512MB, which is enough to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * cover all of lowmem on most platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pci_write_reg(chan, memstart, SH4A_PCIELAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pci_write_reg(chan, (memsize - SZ_256) | 1, SH4A_PCIELAMR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Finish initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) data = pci_read_reg(chan, SH4A_PCIETCTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) data |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pci_write_reg(chan, data, SH4A_PCIETCTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Let things settle down a bit.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) mdelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Enable DL_Active Interrupt generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) data = pci_read_reg(chan, SH4A_PCIEDLINTENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) data |= PCIEDLINTENR_DLL_ACT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pci_write_reg(chan, data, SH4A_PCIEDLINTENR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Disable MAC data scrambling. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) data = pci_read_reg(chan, SH4A_PCIEMACCTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) data |= PCIEMACCTLR_SCR_DIS | (0xff << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) pci_write_reg(chan, data, SH4A_PCIEMACCTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * This will timeout if we don't have a link, but we permit the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * port to register anyways in order to support hotplug on future
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = pci_wait_for_irq(chan, MASK_INT_TX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) data = pci_read_reg(chan, SH4A_PCIEPCICONF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) data &= ~(PCI_STATUS_DEVSEL_MASK << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) data |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) (PCI_STATUS_CAP_LIST | PCI_STATUS_DEVSEL_FAST) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pci_write_reg(chan, data, SH4A_PCIEPCICONF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pci_write_reg(chan, 0x80888000, SH4A_PCIETXVC0DCTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) pci_write_reg(chan, 0x00222000, SH4A_PCIERXVC0DCTLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) data = pci_read_reg(chan, SH4A_PCIEMACSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) printk(KERN_NOTICE "PCI: PCIe#%d x%d link detected\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) port->index, (data >> 20) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) printk(KERN_NOTICE "PCI: PCIe#%d link down\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) port->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) for (i = win = 0; i < chan->nr_resources; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct resource *res = chan->resources + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) resource_size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * We can't use the 32-bit mode windows in legacy 29-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * mode, so just skip them entirely.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) res->flags |= IORESOURCE_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (res->flags & IORESOURCE_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) pci_write_reg(chan, 0x00000000, SH4A_PCIEPTCTLR(win));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * The PAMR mask is calculated in units of 256kB, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * keeps things pretty simple.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) size = resource_size(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) mask = (roundup_pow_of_two(size) / SZ_256K) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pci_write_reg(chan, mask << 18, SH4A_PCIEPAMR(win));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pci_write_reg(chan, upper_32_bits(res->start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) SH4A_PCIEPARH(win));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pci_write_reg(chan, lower_32_bits(res->start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) SH4A_PCIEPARL(win));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) mask = MASK_PARE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (res->flags & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) mask |= MASK_SPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) pci_write_reg(chan, mask, SH4A_PCIEPTCTLR(win));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) win++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int pcibios_map_platform_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return evt2irq(0xae0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) void pcibios_bus_add_device(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dma_direct_set_offset(&pdev->dev, __pa(memory_start),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) __pa(memory_start) - memstart, memsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int __init sh7786_pcie_core_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Return the number of ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return test_mode_pin(MODE_PIN12) ? 3 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static void __init sh7786_pcie_init_hw(void *data, async_cookie_t cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct sh7786_pcie_port *port = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * Check if we are configured in endpoint or root complex mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * this is a fixed pin setting that applies to all PCIe ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) port->endpoint = test_mode_pin(MODE_PIN11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * Setup clocks, needed both for PHY and PCIe registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret = pcie_clk_init(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (unlikely(ret < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) pr_err("clock initialization failed for port#%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) port->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = phy_init(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (unlikely(ret < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pr_err("phy initialization failed for port#%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) port->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret = pcie_init(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (unlikely(ret < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) pr_err("core initialization failed for port#%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) port->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* In the interest of preserving device ordering, synchronize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) async_synchronize_cookie(cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) register_pci_controller(port->hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static struct sh7786_pcie_hwops sh7786_65nm_pcie_hwops __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .core_init = sh7786_pcie_core_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .port_init_hw = sh7786_pcie_init_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int __init sh7786_pcie_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct clk *platclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 mm_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) printk(KERN_NOTICE "PCI: Starting initialization.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) sh7786_pcie_hwops = &sh7786_65nm_pcie_hwops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) nr_ports = sh7786_pcie_hwops->core_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) BUG_ON(nr_ports > ARRAY_SIZE(sh7786_pci_channels));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (unlikely(nr_ports == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) sh7786_pcie_ports = kcalloc(nr_ports, sizeof(struct sh7786_pcie_port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (unlikely(!sh7786_pcie_ports))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * Fetch any optional platform clock associated with this block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * This is a rather nasty hack for boards with spec-mocking FPGAs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * that have a secondary set of clocks outside of the on-chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * ones that need to be accounted for before there is any chance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * of touching the existing MSTP bits or CPG clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) platclk = clk_get(NULL, "pcie_plat_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (IS_ERR(platclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Sane hardware should probably get a WARN_ON.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) platclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) clk_enable(platclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) mm_sel = sh7786_mm_sel();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * Depending on the MMSELR register value, the PCIe0 MEM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * area may not be available. See Table 13.11 of the SH7786
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * datasheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (mm_sel != 1 && mm_sel != 2 && mm_sel != 5 && mm_sel != 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) sh7786_pci0_resources[2].flags |= IORESOURCE_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) printk(KERN_NOTICE "PCI: probing %d ports.\n", nr_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) for (i = 0; i < nr_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct sh7786_pcie_port *port = sh7786_pcie_ports + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) port->index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) port->hose = sh7786_pci_channels + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) port->hose->io_map_base = port->hose->resources[0].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) async_schedule(sh7786_pcie_hwops->port_init_hw, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) async_synchronize_full();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) arch_initcall(sh7786_pcie_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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