^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * New-style PCI core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2004 - 2009 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2002 M. R. Brown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Modelled after arch/mips/pci/pci.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) unsigned long PCIBIOS_MIN_IO = 0x0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned long PCIBIOS_MIN_MEM = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * The PCI controller list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static struct pci_channel *hose_head, **hose_tail = &hose_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int pci_initialized;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static void pcibios_scanbus(struct pci_channel *hose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static int next_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int need_domain_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) LIST_HEAD(resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) resource_size_t offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) bridge = pci_alloc_host_bridge(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) for (i = 0; i < hose->nr_resources; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) res = hose->resources + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (res->flags & IORESOURCE_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (res->flags & IORESOURCE_IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) offset = hose->io_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) else if (res->flags & IORESOURCE_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) offset = hose->mem_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pci_add_resource_offset(&resources, res, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) list_splice_init(&resources, &bridge->windows);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) bridge->dev.parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bridge->sysdata = hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) bridge->busnr = next_busno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bridge->ops = hose->pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) bridge->swizzle_irq = pci_common_swizzle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) bridge->map_irq = pcibios_map_platform_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ret = pci_scan_root_bus_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pci_free_host_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) hose->bus = bridge->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) need_domain_info = need_domain_info || hose->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) hose->need_domain_info = need_domain_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) next_busno = hose->bus->busn_res.end + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Don't allow 8-bit bus number overflow inside the hose -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reserve some space for bridges. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (next_busno > 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) next_busno = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) need_domain_info = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pci_bus_size_bridges(hose->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pci_bus_assign_resources(hose->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pci_bus_add_devices(hose->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * This interrupt-safe spinlock protects all accesses to PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * configuration space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) DEFINE_RAW_SPINLOCK(pci_config_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static DEFINE_MUTEX(pci_scan_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int register_pci_controller(struct pci_channel *hose)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) for (i = 0; i < hose->nr_resources; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct resource *res = hose->resources + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (res->flags & IORESOURCE_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (res->flags & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (request_resource(&ioport_resource, res) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (request_resource(&iomem_resource, res) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) *hose_tail = hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) hose_tail = &hose->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Do not panic here but later - this might happen before console init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!hose->io_map_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pr_warn("registering PCI controller with io_map_base unset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Setup the ERR/PERR and SERR timers, if available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pcibios_enable_timers(hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * Scan the bus if it is register after the PCI subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (pci_initialized) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) mutex_lock(&pci_scan_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pcibios_scanbus(hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mutex_unlock(&pci_scan_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) for (--i; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) release_resource(&hose->resources[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pr_warn("Skipping PCI bus scan due to resource conflict\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int __init pcibios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct pci_channel *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Scan all of the recorded PCI controllers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) for (hose = hose_head; hose; hose = hose->next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pcibios_scanbus(hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pci_initialized = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) subsys_initcall(pcibios_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * We need to avoid collisions with `mirrored' VGA ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * and other strange ISA hardware, so we always want the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * addresses to be allocated in the 0x000-0x0ff region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * modulo 0x400.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) resource_size_t pcibios_align_resource(void *data, const struct resource *res,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) resource_size_t size, resource_size_t align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct pci_dev *dev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct pci_channel *hose = dev->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) resource_size_t start = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (res->flags & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (start < PCIBIOS_MIN_IO + hose->resources[0].start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) start = PCIBIOS_MIN_IO + hose->resources[0].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Put everything into 0x00-0xff region modulo 0x400.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (start & 0x300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) start = (start + 0x3ff) & ~0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pcibios_bus_report_status_early(struct pci_channel *hose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int top_bus, int current_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int status_mask, int warn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned int pci_devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (PCI_FUNC(pci_devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = early_read_config_word(hose, top_bus, current_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pci_devfn, PCI_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ret != PCIBIOS_SUCCESSFUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (status == 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) early_write_config_word(hose, top_bus, current_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pci_devfn, PCI_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) status & status_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (warn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pr_cont("(%02x:%02x: %04X) ", current_bus, pci_devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * We can't use pci_find_device() here since we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * called from interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void __ref
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int warn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) list_for_each_entry(dev, &bus->devices, bus_list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u16 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * ignore host bridge - we handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * that separately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (dev->bus->number == 0 && dev->devfn == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pci_read_config_word(dev, PCI_STATUS, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (status == 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if ((status & status_mask) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* clear the status errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pci_write_config_word(dev, PCI_STATUS, status & status_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (warn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pr_cont("(%s: %04X) ", pci_name(dev), status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) list_for_each_entry(dev, &bus->devices, bus_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (dev->subordinate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pcibios_bus_report_status(dev->subordinate, status_mask, warn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) void __ref pcibios_report_status(unsigned int status_mask, int warn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct pci_channel *hose;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) for (hose = hose_head; hose; hose = hose->next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (unlikely(!hose->bus))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pcibios_bus_report_status_early(hose, hose_head->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) hose->index, status_mask, warn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pcibios_bus_report_status(hose->bus, status_mask, warn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #ifndef CONFIG_GENERIC_IOMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void __iomem *__pci_ioport_map(struct pci_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned long port, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct pci_channel *chan = dev->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (unlikely(!chan->io_map_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) chan->io_map_base = sh_io_port_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (pci_domains_supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) panic("To avoid data corruption io_map_base MUST be "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "set with multiple PCI domains.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return (void __iomem *)(chan->io_map_base + port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) iounmap(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) EXPORT_SYMBOL(pci_iounmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif /* CONFIG_GENERIC_IOMAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) EXPORT_SYMBOL(PCIBIOS_MIN_IO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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