Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *	Low-Level PCI Support for SH7780 targets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Dustin McIntire (dustin@sensoria.com) (c) 2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Paul Mundt (lethal@linux-sh.org) (c) 2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef _PCI_SH7780_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _PCI_SH7780_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* SH7780 Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define	PCIECR			0xFE000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PCIECR_ENBL		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* SH7780 Specific Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SH7780_PCI_CONFIG_BASE	0xFD000000	/* Config space base addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SH7780_PCI_CONFIG_SIZE	0x01000000	/* Config space size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SH7780_PCIREG_BASE	0xFE040000	/* PCI regs base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* SH7780 PCI Config Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SH7780_PCIIR		0x114		/* PCI Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SH7780_PCIIMR		0x118		/* PCI Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SH7780_PCIAIR		0x11C		/* Error Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SH7780_PCICIR		0x120		/* Error Command/Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SH7780_PCIAINT		0x130		/* Arbiter Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SH7780_PCIAINTM		0x134		/* Arbiter Int. Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SH7780_PCIBMIR		0x138		/* Error Bus Master Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SH7780_PCIPAR		0x1C0		/* PIO Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SH7780_PCIPINT		0x1CC		/* Power Mgmnt Int. Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SH7780_PCIPINTM		0x1D0		/* Power Mgmnt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SH7780_PCIMBR(x)	(0x1E0 + ((x) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SH7780_PCIMBMR(x)	(0x1E4 + ((x) * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SH7780_PCIIOBR		0x1F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SH7780_PCIIOBMR		0x1FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SH7780_PCICSCR0		0x210		/* Cache Snoop1 Cnt. Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SH7780_PCICSCR1		0x214		/* Cache Snoop2 Cnt. Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SH7780_PCICSAR0		0x218	/* Cache Snoop1 Addr. Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SH7780_PCICSAR1		0x21C	/* Cache Snoop2 Addr. Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #endif /* _PCI_SH7780_H_ */