^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Low-Level PCI Support for the SH7751
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003 - 2009 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2001 Dustin McIntire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * With cleanup by Paul van Gool <pvangool@mimotech.com>, 2003.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pci-sh4.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static int __init __area_sdram_check(struct pci_channel *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned int area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) unsigned long word;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) word = __raw_readl(SH7751_BCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* check BCR for SDRAM in area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) if (((word >> area) & 1) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) area, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) pci_write_reg(chan, word, SH4_PCIBCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) word = __raw_readw(SH7751_BCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* check BCR2 for 32bit SDRAM interface*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (((word >> (area << 1)) & 0x3) != 0x3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) area, word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) pci_write_reg(chan, word, SH4_PCIBCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct resource sh7751_pci_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .name = "SH7751_IO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .start = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .end = SZ_4M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .flags = IORESOURCE_IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .name = "SH7751_mem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .start = SH7751_PCI_MEMORY_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .flags = IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct pci_channel sh7751_pci_controller = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .pci_ops = &sh4_pci_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .resources = sh7751_pci_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .nr_resources = ARRAY_SIZE(sh7751_pci_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .mem_offset = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .io_offset = 0x00000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .io_map_base = SH7751_PCI_IO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static struct sh4_pci_address_map sh7751_pci_map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .window0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .base = SH7751_CS3_BASE_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .size = 0x04000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int __init sh7751_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct pci_channel *chan = &sh7751_pci_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 word, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) printk(KERN_NOTICE "PCI: Starting initialization.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) chan->reg_base = 0xfe200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* check for SH7751/SH7751R hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) id = pci_read_reg(chan, SH7751_PCICONF0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Set the BCR's to enable PCI access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) reg = __raw_readl(SH7751_BCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reg |= 0x80000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __raw_writel(reg, SH7751_BCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Turn the clocks back on (not done in reset)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pci_write_reg(chan, 0, SH4_PCICLKR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Clear Powerdown IRQ's (not done in reset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pci_write_reg(chan, word, SH4_PCIPINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* set the command/status bits to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Wait Cycle Control + Parity Enable + Bus Master +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Mem space enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pci_write_reg(chan, word, SH7751_PCICONF1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* define this host as the host bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) word = PCI_BASE_CLASS_BRIDGE << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pci_write_reg(chan, word, SH7751_PCICONF2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Set IO and Mem windows to local address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Make PCI and local address the same for easy 1 to 1 mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) word = sh7751_pci_map.window0.size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pci_write_reg(chan, word, SH4_PCILSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Set the values on window 0 PCI config registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) word = P2SEGADDR(sh7751_pci_map.window0.base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pci_write_reg(chan, word, SH4_PCILAR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pci_write_reg(chan, word, SH7751_PCICONF5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Set the local 16MB PCI memory space window to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * the lowest PCI mapped address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) word = chan->resources[1].start & SH4_PCIMBR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pci_write_reg(chan, word , SH4_PCIMBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Make sure the MSB's of IO window are set to access PCI space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) word = chan->resources[0].start & SH4_PCIIOBR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pci_write_reg(chan, word, SH4_PCIIOBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Set PCI WCRx, BCRx's, copy from BSC locations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* check BCR for SDRAM in specified area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) switch (sh7751_pci_map.window0.base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(chan, 3); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(chan, 4); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(chan, 5); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(chan, 6); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!word)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* configure the wait control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) word = __raw_readl(SH7751_WCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pci_write_reg(chan, word, SH4_PCIWCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) word = __raw_readl(SH7751_WCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pci_write_reg(chan, word, SH4_PCIWCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) word = __raw_readl(SH7751_WCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pci_write_reg(chan, word, SH4_PCIWCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) word = __raw_readl(SH7751_MCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) pci_write_reg(chan, word, SH4_PCIMCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* NOTE: I'm ignoring the PCI error IRQs for now..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * TODO: add support for the internal error interrupts and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * DMA interrupts...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pci_fixup_pcic(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* SH7751 init done, set central function init complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* use round robin mode to stop a device starving/overruning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pci_write_reg(chan, word, SH4_PCICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return register_pci_controller(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) arch_initcall(sh7751_pci_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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